Transformational ML-Based Approach to Tackle Severe FPGA Placement and Routing Failures

Placement and routing failures during the FPGA backend flow are frequent with many FPGA designs especially when these involve multiple physical constraints. This paper introduces the Machine-Learning-based approach implemented in InTime toolset to transform these failures to a less complex problem of timing convergence. Thanks to machine learning, InTime can identify the root causes of the placement or the routing failures, mitigating them through adjustment of the user constraints, and setting the various options making the design placement and routing friendly. As the experimental results illustrate, the encountered placement and routing failures are all resolved. Additionally, timing requirements are met for over 85% of the case through this ML-based transformation. The other 15% of the designs are processed through the traditional InTime recipes to resolve timing convergence.

Topics covered in this whitepaper

• Inherent and Artificial Root Causes of Placement and Routing Failures
• Auto ML-Based Approach to Tackle Placement and Routing Failures
• Auto ML-Based Approach Experimental Results
• Final Look and Ongoing Near Future and Mid-Term Development

Timing performance comparison between InTime default recipe and seed sweep

This whitepaper compares the effectiveness of two timing optimization methods: The InTime Default recipe provided by the InTime FPGA design optimization tool and another one commonly known as a “Seed Sweep”. As a result, InTime is more effective at delivering higher timing performance, and there are even greater performance improvements if both methods are used in conjunction – namely, by doing a Seed Sweep based on good InTime Default results.

Topics covered in this whitepaper

• Introduction of InTime Default recipe and seed sweep, and information of the comparison experiments.
• Design details of the experiments.
• Test procedures.
• Experimentation results.
• Optimization Process and run time.
• Conclusion.

InTime Timing Closure Methodology for Quartus

The InTime Timing Closure Methodology is a set of best practices and guidelines to determine the best build parameters under the condition that the design is currently immutable, i.e. you cannot change your RTL or constraints. InTime uses machine learning principles to achieve timing closure or optimization, treating the FPGA synthesis and place-and-route tools as black boxes and analyzing design performance across a whole range of build parameter variations. The guidelines in this document will help you achieve your performance goals in the minimum number of compilations and fastest turnaround time possible.

Topics covered in this whitepaper

• Understanding the InTime Optimization Phases and InTime Optimization Process
• Recipe Selection  and Parameter Selection
• Achieve Faster Convergence of Results
• Likelihood of Meeting Timing
• Minimize Run Time with Timing Estimates

InTime Timing Closure Methodology for Vivado

The InTime Timing Closure Methodology is a set of best practices and guidelines to determine the best build parameters under the condition that the design is currently immutable, i.e. you cannot change your RTL or constraints. InTime uses machine learning principles to achieve timing closure or optimization, treating the FPGA synthesis and place-and-route tools as black boxes and analyzing design performance across a whole range of build parameter variations. The guidelines in this document will help you achieve your performance goals in the minimum number of compilations and fastest turnaround time possible.

Topics covered in this whitepaper

• Understanding the InTime Optimization Phases and InTime Optimization Process
• Recipe Selection  and Parameter Selection
• Achieve Faster Convergence of Results
• Likelihood of Meeting Timing
• Minimize Run Time with Timing Estimates

Timing closure in FPGAs is critical

If you are reading this, the odds are that you or someone in your company is facing / has faced FPGA design challenges. Timing closure is the single most important obstacle to implementing a successful FPGA application.

Bruce Talley, former VP of Software at Xilinx and Plunify technical advisor, is one of the most qualified people to speak about this topic. Download the whitepaper to view his perspectives.

Topics covered in this whitepaper

• Planning for timing closure.
• The vendor tools do a remarkably good job at design compilation for the general case but sometimes they can fall short.
• Why is timing closure so difficult for the vendor FPGA compilation tools?
• What to do if you cannot achieve timing closure?
• How does the InTime timing closure tool help?

Optimizing design performance with Xilinx tools in InTime

This whitepaper describes how InTime works with Vivado to optimize FPGA timing performance by adjusting compilation parameters and running builds in parallel. InTime uses machine learning to determine the best combination of synthesis and place-&-route settings for a FPGA design. Combined with compute servers, InTime rapidly optimizes timing while simultaneously addressing limitations on the user’s flow automation.

Topics covered in this whitepaper

• Introduction of traditional timing closure techniques and InTime’s approach.
• Understanding the InTime flow.
• Steps to optimize a design using InTime.
• InTime & Vivado in the cloud.