InTime – FPGA Timing Closure & Optimization

Reduce Months of Design Iterations to Days

InTime has built-in intelligence to predict optimized strategies for synthesis, placement and routing. It uses machine learning to actively learn from past results, improving the predictions over time. InTime can extract more than 50% increase in design performance from the FPGA tools.

Get to Timing Closure without RTL Changes

High resource utilization often leads to place-&-route timing issues. Or a 3rd-party IP that cannot be edited causes issues in the middle of a tight deadline. Sometimes it is just plain old “whack-a-mole” timing paths.

It is simply impractical to rip up and re-optimize your RTL all the time. Use InTime-optimized settings and constraints to achieve your timing without changing RTL.

Reuse Results and Reduce Turnaround Time

Previous build results, good or bad, are valuable. From re-running previously generated settings to using incremental compilation, newer design revisions can benefit from older builds without going through the entire learning process again. Of course, the more builds InTime does, the higher the likelihood of a better result becomes.

Analyse & Troubleshoot Across Builds

InTime analytics help you understand results and problems across multiple builds, instead of narrowly looking at a single build. From measuring logic vs. routing delays across “Common Critical Paths” (CCP) to “Errors and Warnings” analytics, the tool provides additional clarity on the design characteristics.

InTime UI_FPGA Close Timing_for Xilinx, Altera_AWS

Faster Results over the Network

InTime works locally or on multiple computers in a network, distributing builds and aggregating results across machines automatically. It is integrated with resource management software like LSF or SGE. With Plunify Cloud, you can even offload builds to AWS without being a cloud expert. Read more about running InTime in the cloud.

FPGA-specific Optimizations

InTime supports major FPGA tools such as Quartus Prime, Vivado, ISE and Libero. Vendor- and architecture-specific optimizations are created for Xilinx , Intel and Microchip. These optimizations tackle different devices, design characteristics, floor planning and routing problems. Think of InTime as your personal support engineer.

InTime Screenshots

Supported FPGA Tools


Read more about InTime success story