InTime is a machine learning software that optimizes FPGA timing and performance using analytics and compute power.
FPGA tools such as Vivado, Quartus and ISE provide massive optimization benefits with the right settings and techniques. InTime has built-in intelligence to identify such optimized strategies for synthesis and place-and-route. It actively learns from results to improve over time, extracting more than 50% increase in design performance from the FPGA tools.
Get better results without modifying your design RTL or constraints. It could be a third party IP that you cannot edit or tight deadlines to meet. We know it is not practical all the time to rip up and re-optimize your RTL.
Let InTime analyze your FPGA design and determine optimized settings and constraints for synthesis and place-and-route.
Previous build results can be learned from and used to improve subsequent ones based on device, design and tool characteristics. The more builds InTime does, the higher the likelihood of a better result becomes.
With machine learning, InTime gets smarter every time it runs. And you can even build your own internal machine learning databases conveniently with ease.
Seed sweep is a well-known technique to get additional performance from placement changes. Beyond just seed sweeps, InTime uses tool settings and placement optimizations to achieve better timing and area performance for your design. To understand why this is a powerful tool, check out our whitepaper comparing timing performance of these methods.
InTime assimilates the computers you use into one big grid, distributing builds and aggregating results across machines automatically. It works well with resource management software like LSF or SGE. You can run InTime on-premise in your company’s data center or in the cloud. Read more about running InTime in the cloud.
Plunify is a trusted partner of Xilinx and Intel. FPGA tools such as Quartus Prime, Vivado, and ISE, give tremendous optimization gains with the appropriate settings and techniques. Every result that you get in InTime is derived from these tools. You can also export any InTime result back to the FPGA tools to verify its accuracy.