Press Releases

Plunify Closes Funding Round to Enhance FPGA Design Timing Closure Capabilities


Funds will be used to scale operations and drive further growth in Asia and North America

SINGAPORE – April 27, 2016 – Plunify® Pte. Ltd., provider of FPGA timing closure and design optimization software for the semiconductor chip design industry, today announced it completed a round of funding with an investment from Kumpulan Modal Perdana (KMP), a Malaysian venture capital and investment firm specializing in cutting-edge engineering technologies.

The investment will be used to scale Plunify’s sales and technical support channels, as well as extend its marketing reach to promote its InTime software and educate FPGA design companies on how to use InTime to solve design problems and speed up their products’ Time to Market.

“What we see in Plunify is something well ahead of current solutions in terms of the innovation and problem-solving capabilities that the company is bringing to market,” said Shahril Anwar, chief executive officer of KMP.

Plunify’s InTime Timing Closure Acceleration Software

Plunify’s InTime timing closure acceleration software produces better results faster. It analyzes an FPGA design and determines the best synthesis and place-and-route optimization strategies, taking into account correlations between the design structure, FPGA resources and the design constraints. InTime highlights specific sections of the design where timing errors occur, enabling engineers to quickly diagnose and fix problems. The tool uses proprietary statistical modeling and big data techniques, analyzing designs to solve FPGA timing and optimization problems. InTime also employs machine learning to draw insights from designs to improve quality of results. The software has a unique ability to learn and accumulate knowledge about a user’s design that can be applied to subsequent designs.

“Every design is unique in its merits and also in its flaws. Our algorithms and data models exploit such insights to solve customers’ problems,” notes Harnhua Ng, Plunify’s chief executive officer. “KMP is extremely supportive and is providing invaluable resources and advice on scaling our operations worldwide. We welcome their experience and advice.”

Major FPGA customers like Huawei and Fiberhome are using InTime to meet timing on designs that used to fail by thousands of nanoseconds, accelerating their typical project completion time by more than 25%.

About Plunify 

Solutions from Plunify® Pte. Ltd. enable semiconductor chip designers to shorten product time to market and reduce development costs with no disruption to existing workflows. Its EDAxtend™ chip design platform and InTime™ timing closure tool help electronics companies meet FPGA design performance targets and significantly reduce their products’ time to market. For more on Plunify’s products, visit