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Got FPGA Timing Closure Problems?

Watch Plunify’s webinar to learn how to solve your most difficult timing problems.

Date: 10 March 2015
Time: 10am (Pacific Standard Time)

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Estimated Length: 40 Minutes + 10 Minutes Q&A

Who Should Attend: FPGA designers, project leaders, and engineering managers

Attendees Will: See examples of the typical causes of FPGA timing closure issues. Learn how “machine learning” tools solve these timing closure problems without changing the RTL source code. Interact with Plunify’s InTime timing closure tool via a live demo. Have access to FPGA and EDA timing closure experts for Q&A. Learn about Plunify’s “Results-Based or Free” Pricing Model for FPGA design optimization services.

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Upcoming Events

Visit us at FPGA 2015

23rd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

Monterey Conference Center
Monterey, California
February 22 - 24, 2015


Regression Testing
Timing Closure
Design Optimization
Design Space Exploration
Resource Management
Hardware design teams need to see if an existing design works when different parameters are applied, for example different FPGA software tool versions or changes in adjacent non-FPGA modules. Such regressions involve running multiple test vectors to quickly detect if something broke as a result of the changes.

Plunify helps design engineers set up and execute regression workflows to evaluate many different scenarios.

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Analyzing critical paths, modifying a design and re-compiling are critical, iterative steps in getting a design to meet timing. Both the design engineer’s expertise and short build turnaround times are critical in solving problems.

Plunify helps design engineers execute and analyze multiple timing closure attempts in parallel, speeding up design closure efforts.

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Reducing power, increasing maximum frequency, lowering area utilization are optimization goals that design engineers aim for after getting a design to work. Changes in timing may have effects on area or power so balancing tradeoffs while maximizing primary objectives is a priority.

Experimenting with different FPGA software tool options or vary the clock logic in RTL.

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In the initial stages of a design, hardware decisions have not been finalized, and design engineers may want to explore different device families, speed grades and IP modules parameters. The results of these evaluations affect how the product is tested and deployed eventually.

Set up and run such experiments in parallel to gather data and make informed decisions.

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Insufficient servers / licenses and packed job queues are IT factors that cause delays, which are exacerbated during periods of peak demand when everyone is trying to run builds. Plunify helps design teams manage and scale compute demands, providing FPGA synthesis and place-and-route on a pay-as-you-use basis, alleviating concerns about IT over-investment and under-investment.

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