InTime® is an expert software that solves FPGA timing and optimization problems with massive computing power and machine learning.
InTime has built-in intelligence to analyze an FPGA design and determine optimized strategies for synthesis and place-and-route. Based on knowledge of device, design and tool characteristics and proprietary algorithms, InTime generates settings and design constraints that have the highest chances of meeting design performance targets. By intelligently harnessing computing resources, either from a private or public cloud, InTime enables FPGA engineers to solve design problems significantly faster than before.Download the datasheet
Intelligient and automatic generation of build strategies
InTime’s signature database stores knowledge from over 50,000 CPU hours of benchmarking across multiple tool versions and device families. This enables InTime to tailor tool settings and constraints for specific design conditions.
Advanced result analysis
InTime’s result analytics enables users to compare multiple builds at a glance to find similarities between passing builds and pinpoint causes of failure.
User interface optimized for design flows
Both graphical user interfaces and a scriptable Tcl API are available depending on users’ needs. InTime integrates readily with existing flows.
Automatically run multiple builds in parallel
In a multi-machine configuration, a designated InTime "control" server allocates machines for every "job" (consisting of one or more builds). InTime communicates with the "worker" machines, encrypting and transferring files/results.
Manage clients, automatically detect availability
The control server’s management console monitors and keeps track of all worker machines and resources, including legacy designs and tool versions which are archived for use when required.
on worker machine(s)
Easily pause and
|Comprehensive job management and audit logs|
|To prevent system slowdown, InTime automatically queues builds and runs them only as resources are freed up.||Users can restart a job from where it left off (e.g. unexpected crash), either from the InTime client or from the management console.||Each job generates a set of diagnostic logs used for detecting and debugging problems as well as keeping a detailed audit of usage.|
Collate and visualize job results across network
InTime automatically collates build results across the network and present them in intuitive charts and tables. See everything in one glance without figuring out which result on is which machine. The data comes to you.
Run multiple builds in parallel
Timing closure, regression testing, design space exploration and many other design steps require many iterations and long builds. Why wait? Plunify enables you to customize and run multiple builds in parallel with simple commands, saving you massive amount of time and effort.
Lightweight and Secure
Small yet powerful. Downloaded in minutes, our script packages and encrypts your files with keys unique to you. All your data is transmitted only in a secured SSL channel to a dedicated location for added peace of mind. Click here to read more about our security. For more details, please feel free to contact us
Intuitive and Graphical Results
Compared to a full EDA software installation, FPGAAccel Client is easy to use and does not come with complex interfaces or lengthy user manuals. Viewing and downloading the results is just as easy. Leave the analysis to us and use our web report viewer to view your results in a graphical and intuitive manner.
Supports Netlist Files
To balance a need for higher security with upload speed/convenience, FPGAAccel Client accepts netlist files instead of RTL files. This means users can synthesize the design locally and send only netlist files. All files are still encrypted by default and place-&-route will be executed in the cloud. Your runtime in the cloud will be shorter as well.
No downloads, installation or setup. Experience a full FPGA design compilation online with just your browser. Start with either source files or netlists. You have the freedom to select multiple devices and different tool versions.
Your results appear on a highly graphical and intuitive charts. And you can download all the log files if you want to analyse it better. With no downloads, you can start your FPGA project in minutes.
Just you and your browser
No downloads, installations, configurations or any maintenance - it is that easy to get started! Just use your browser, sign up and you are ready to go. Our web tool gives chip designers a quick and fast way to access chip design tools from any computer or mobile device. Click here to sign up
Full Encryption and Secure Transmission
All your data is transmitted in a secured SSL channel to a dedicated location for added peace of mind. It is also encrypted using AES before storage. Each account uses dedicated servers for processing and no data is shared. Click here to read more about our security mechanisms. For additional details, please feel free to contact us.
Supports Legacy Tool Versions
We know that supporting legacy products and tool versions can be a big pain and hassle. That's why you can just click and choose the software tools you want on FPGAAccel Web, and we will launch a server with the right software. No more maintenance or keeping backup copies - we do all that for you. Click here to find out what versions we support
A more-optimized product requires detailed knowledge of the different types of devices available, for example their features and characteristics. FPGAAccel Web enables designers to target multiple devices at the same time, helping to easily find out how the design fits into different devices and to pick the best one for the project.