[vc_row row_type=”row” stretch_row_type=”no”][vc_column][vc_column_text css=”.vc_custom_1523585054095{margin-top: 65px !important;margin-bottom: 65px !important;}”]<\/p>\n
[\/vc_column_text][vc_row_inner][vc_column_inner width=”2\/3″][vc_single_image image=”4635″ img_size=”large”][\/vc_column_inner][vc_column_inner width=”1\/3″][vc_column_text css=”.vc_custom_1562813958423{background-position: center !important;background-repeat: no-repeat !important;background-size: cover !important;}”]<\/p>\n
[\/vc_column_text][vc_column_text]High resource utilization often leads to place-&-route timing issues. Or a 3rd-party IP that cannot be edited causes issues in the middle of a tight deadline. Sometimes it is just plain old “whack-a-mole” timing paths. <\/span><\/p>\n It is simply impractical to rip up and re-optimize your RTL all the time.<\/span> Use InTime-optimized settings and constraints to achieve your timing without changing RTL. [\/vc_column_text][vc_column_text]Previous build results, good or bad, are valuable. From re-running previously generated settings to using incremental compilation, newer design revisions can benefit from older builds without going through the entire learning process again. Of course, the more builds InTime does, the higher the likelihood of a better result becomes.<\/span>[\/vc_column_text][\/vc_column_inner][\/vc_row_inner][vc_empty_space height=”60px”][vc_separator color=”chino” style=”shadow”][vc_empty_space height=”50px”][vc_row_inner][vc_column_inner width=”1\/2″][vc_column_text css_animation=”left-to-right”]<\/p>\n [\/vc_column_text][vc_column_text]Starting in InTime 2022,\u00a0 InTime offers an automated, congestion-aware floorplanning approach. Placement and routing engines of major FPGA tools are well-tuned and robust enough in most cases. However, these engines are often inadequate for designs with high utilization and\/or congestion. Floorplanning is necessary to guide these engines to provide better Place & Route results. [\/vc_column_text][vc_column_text]InTime analytics help you understand results and problems across multiple builds, instead of narrowly looking at a single build. From measuring logic vs. routing delays across “Common Critical Paths” (CCP) to “Errors and Warnings” analytics, the tool provides additional clarity on the design characteristics. [\/vc_column_text][vc_column_text]InTime works locally or on multiple computers in a network, distributing builds and aggregating results across machines automatically. It is integrated with resource management software like LSF<\/a><\/span> or SGE<\/a><\/span>. With Plunify Cloud, you can even offload builds to AWS without being a cloud expert. Read more<\/a> about running InTime in the cloud.<\/span><\/p>\n [\/vc_column_text][\/vc_column_inner][\/vc_row_inner][vc_empty_space height=”30px”][vc_separator color=”chino” style=”shadow” css=”.vc_custom_1531109447824{margin-top: 0px !important;margin-bottom: 0px !important;}”][vc_row_inner content_placement=”middle”][vc_column_inner][vc_column_text]<\/p>\n [\/vc_column_text][\/vc_column_inner][\/vc_row_inner][\/vc_column][\/vc_row][vc_row row_type=”row” stretch_row_type=”no”][vc_column][vc_empty_space height=”60px”][vc_column_text]<\/p>\n [\/vc_column_text][vc_column_text]InTime supports major FPGA tools such as\u00a0Quartus Prime<\/a>, Vivado<\/a>, ISE<\/a>\u00a0and Libero<\/a>. Vendor- and architecture-specific optimizations are created for Xilinx <\/a>, Intel<\/a>\u00a0and Microchip<\/a>. These optimizations tackle different devices, design characteristics, floor planning and routing problems. Think of InTime as your personal support engineer.<\/span>[\/vc_column_text][vc_row_inner][vc_column_inner width=”1\/4″][vc_single_image image=”4665″ img_size=”235×80″ alignment=”center” css=”.vc_custom_1620696059540{padding-left: 5px !important;}”][\/vc_column_inner][vc_column_inner width=”1\/4″][vc_single_image image=”1227″ img_size=”138×90″ alignment=”center”][\/vc_column_inner][vc_column_inner width=”1\/4″][vc_single_image image=”1879″ img_size=”medium” alignment=”center”][\/vc_column_inner][vc_column_inner width=”1\/4″][vc_single_image image=”4856″ img_size=”full” alignment=”right”][\/vc_column_inner][\/vc_row_inner][\/vc_column][\/vc_row][vc_row row_type=”row” stretch_row_type=”no”][vc_column][vc_empty_space height=”10px”][vc_row_inner][vc_column_inner width=”1\/6″][\/vc_column_inner][vc_column_inner width=”2\/3″][vc_column_text]<\/p>\n
\nInTime has built-in intelligence to predict optimized strategies for synthesis, placement and routing. It uses machine learning to actively learn from past results, improving the predictions over time. InTime can extract more than 50% increase<\/a> in design performance from the FPGA tools.
\n<\/span>[\/vc_column_text][\/vc_column_inner][\/vc_row_inner][vc_empty_space height=”10px”][vc_separator color=”chino” style=”shadow”][vc_empty_space height=”50px”][vc_row_inner][vc_column_inner width=”1\/2″ css=”.vc_custom_1486631727673{margin-bottom: 50px !important;}”][vc_column_text css_animation=”left-to-right”]<\/p>\nGet to Timing Closure without RTL Changes<\/span><\/h1>\n
\n<\/span>[\/vc_column_text][\/vc_column_inner][vc_column_inner width=”1\/2″][vc_single_image image=”3527″ img_size=”full”][\/vc_column_inner][\/vc_row_inner][vc_empty_space height=”60px”][vc_separator color=”chino” style=”shadow”][vc_empty_space height=”50px”][\/vc_column][\/vc_row][vc_row row_type=”row” stretch_row_type=”no”][vc_column][vc_row_inner][vc_column_inner width=”1\/2″ css=”.vc_custom_1562638798101{margin-top: 10px !important;}”][vc_single_image image=”4613″ img_size=”large”][\/vc_column_inner][vc_column_inner width=”1\/2″][vc_column_text css_animation=”right-to-left”]<\/p>\nReuse Results and Reduce Turnaround Time
\n<\/span><\/h1>\nFloorplanning Automation
\n<\/span><\/h1>\n
\n<\/span>[\/vc_column_text][vc_btn title=”Learn More” color=”success” link=”url:https%3A%2F%2Fwww.plunify.com%2Fen%2Fintime%2Ffloorplanning%2F|||”][\/vc_column_inner][vc_column_inner width=”1\/2″][vc_single_image image=”4956″ img_size=”large”][\/vc_column_inner][\/vc_row_inner][vc_empty_space height=”60px”][vc_separator color=”chino” style=”shadow”][vc_empty_space height=”30px”][vc_column_text css_animation=”left-to-right”]<\/p>\nAnalyse & Troubleshoot Across Builds
\n<\/span><\/h1>\n
\n<\/span>[\/vc_column_text][vc_row_inner][vc_column_inner width=”1\/2″][vc_single_image image=”4649″ img_size=”large”][\/vc_column_inner][vc_column_inner width=”1\/2″][vc_single_image image=”4617″ img_size=”large”][\/vc_column_inner][\/vc_row_inner][vc_empty_space height=”60px”][vc_separator color=”chino” style=”shadow”][vc_empty_space height=”50px”][vc_row_inner][vc_column_inner width=”1\/4″][vc_single_image image=”1269″ img_size=”337×306″ alignment=”center” css=”.vc_custom_1500280315248{margin-top: 20px !important;}”][\/vc_column_inner][vc_column_inner width=”3\/4″][vc_column_text css_animation=”right-to-left”]<\/p>\nFaster Results over the Network
\n<\/span><\/h1>\nInTime Screenshots<\/h2>\n
Supported FPGA Tools<\/h2>\n