{"id":3469,"date":"2018-05-10T17:42:01","date_gmt":"2018-05-10T09:42:01","guid":{"rendered":"https:\/\/www.plunify.com\/en\/?page_id=3469"},"modified":"2019-02-08T12:15:46","modified_gmt":"2019-02-08T04:15:46","slug":"fpga-timing-closure-congested-test-measurement-designs-machine-learning","status":"publish","type":"page","link":"https:\/\/www.plunify.com\/en\/fpga-timing-closure-congested-test-measurement-designs-machine-learning\/","title":{"rendered":"FPGA Timing Closure for Congested Test &amp; Measurement Designs &#8211; A Machine Learning Solution"},"content":{"rendered":"<p>[vc_row row_type=&#8221;row&#8221; stretch_row_type=&#8221;no&#8221;][vc_column][vc_column_text]FPGAs are widely used in the Test and Measurement (T&amp;M) industry for their capabilities in high-speed signal processing, high precision data processing, and general design flexibility. As market demand for faster and more precise instrumentation increases, T&amp;M FPGA designs also become more complex and more challenging in terms of timing closure &#8211; directly impacting Time-to-Market.<\/p>\n<p>This article discusses how a new design optimization approach known as the\u00a0<a href=\"https:\/\/www.plunify.com\/en\/wp-content\/uploads\/sites\/8\/2018\/05\/InTime-Timing-Closure-Methodology-for-Vivado-WP04.pdf\" target=\"_blank\" rel=\"noopener\">InTime Timing Closure Methodology<\/a> was recently used to increase the FMax, as well as to optimize and close timing for five large, routing-congested T&amp;M designs <span style=\"text-decoration: underline;\">within a week<\/span>. Based on machine learning, this new approach is baked into the <a href=\"https:\/\/www.plunify.com\/en\/intime\/\" target=\"_blank\" rel=\"noopener\">InTime<\/a> design optimization software tool.<\/p>\n<h3>Design Background<\/h3>\n<p><strong>Device:\u00a0<\/strong>Xilinx Virtex Ultrascale xcvu190<\/p>\n<p>Although FPGA resource utilization was relatively low, numerous SLR crossings and high routing congestion make it difficult to reduce the number of failing paths in these designs. The estimated routing congestion for one of the T&amp;M designs:<\/p>\n<pre style=\"text-align: center;\">INFO: [Route 35-449] Initial Estimated Congestion\r\n________________________________________________________________________\r\n|\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 | Global Congestion | Long Congestion\u00a0\u00a0 | Short Congestion\u00a0 |\r\n|\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 |___________________|___________________|___________________|\r\n| Direction | Size\u00a0\u00a0 | % Tiles\u00a0 | Size\u00a0\u00a0 | % Tiles\u00a0 | Size\u00a0\u00a0 | % Tiles\u00a0 |\r\n|___________|________|__________|________|__________|________|__________|\r\n|\u00a0\u00a0\u00a0\u00a0\u00a0 NORTH|\u00a0\u00a0 64x64|\u00a0\u00a0\u00a0\u00a0\u00a0 3.53|\u00a0\u00a0 32x32|\u00a0\u00a0\u00a0\u00a0\u00a0 6.04|\u00a0\u00a0 64x64|\u00a0\u00a0\u00a0\u00a0\u00a0 6.29|\r\n|___________|________|__________|________|__________|________|__________|\r\n|\u00a0\u00a0\u00a0\u00a0\u00a0 SOUTH|\u00a0\u00a0 64x64|\u00a0\u00a0\u00a0\u00a0\u00a0 6.64|\u00a0\u00a0 64x64|\u00a0\u00a0\u00a0\u00a0\u00a0 8.08|\u00a0\u00a0 64x64|\u00a0\u00a0\u00a0\u00a0\u00a0 8.43|\r\n|___________|________|__________|________|__________|________|__________|\r\n|\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 EAST|\u00a0\u00a0 32x32|\u00a0\u00a0\u00a0\u00a0\u00a0 2.41|\u00a0\u00a0 16x16|\u00a0\u00a0\u00a0\u00a0\u00a0 1.85|\u00a0\u00a0 32x32|\u00a0\u00a0\u00a0\u00a0\u00a0 6.72|\r\n|___________|________|__________|________|__________|________|__________|\r\n|\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 WEST|\u00a0\u00a0 64x64|\u00a0\u00a0\u00a0\u00a0\u00a0 4.26|\u00a0\u00a0 32x32|\u00a0\u00a0\u00a0\u00a0\u00a0 2.92|\u00a0128x128|\u00a0\u00a0\u00a0\u00a0 14.73|\r\n|___________|________|__________|________|__________|________|__________|<\/pre>\n<h3>Before &amp; After InTime Optimization<\/h3>\n<p>Here are the FMax Improvements.\u00a0 You can see that there are between 23% to 79.7% improvements in FMax using this method.<\/p>\n<p><img loading=\"lazy\" class=\"aligncenter wp-image-3527 size-full\" src=\"https:\/\/www.plunify.com\/en\/wp-content\/uploads\/sites\/8\/2018\/05\/FMax_improvements.png\" alt=\"FMax_improvements\" width=\"797\" height=\"461\" srcset=\"https:\/\/www.plunify.com\/en\/wp-content\/uploads\/sites\/8\/2018\/05\/FMax_improvements.png 797w, https:\/\/www.plunify.com\/en\/wp-content\/uploads\/sites\/8\/2018\/05\/FMax_improvements-300x174.png 300w, https:\/\/www.plunify.com\/en\/wp-content\/uploads\/sites\/8\/2018\/05\/FMax_improvements-768x444.png 768w\" sizes=\"(max-width: 797px) 100vw, 797px\" \/><\/p>\n<p>&nbsp;<\/p>\n<table style=\"height: 252px;\" width=\"795\">\n<tbody>\n<tr>\n<td style=\"text-align: center;\" width=\"64\"><strong>Project Name<\/strong><\/td>\n<td style=\"text-align: center;\" width=\"90\"><strong>WNS (Before)<\/strong><\/td>\n<td style=\"text-align: center;\" width=\"82\"><strong>WNS (After)<\/strong><\/td>\n<td style=\"text-align: center;\" width=\"89\"><strong>TNS (Before)<\/strong><\/td>\n<td style=\"text-align: center;\" width=\"64\"><strong>TNS (After)<\/strong><\/td>\n<td style=\"text-align: center;\" width=\"107\"><strong>WNS Improvements<\/strong><\/td>\n<td style=\"text-align: center;\" width=\"130\"><strong>TNS<\/strong><br \/>\n<strong> Improvements<\/strong><\/td>\n<td style=\"text-align: center;\" width=\"90\"><strong>FMax (Before)<\/strong><\/td>\n<td style=\"text-align: center;\" width=\"80\"><strong>FMax (After)<\/strong><\/td>\n<\/tr>\n<tr>\n<td style=\"text-align: center;\" width=\"64\">A<\/td>\n<td style=\"text-align: center;\" width=\"90\">-0.854<\/td>\n<td style=\"text-align: center;\" width=\"82\">-0.217<\/td>\n<td style=\"text-align: center;\" width=\"89\">-16961.285<\/td>\n<td style=\"text-align: center;\" width=\"64\">-582.23<\/td>\n<td style=\"text-align: center;\" width=\"107\"><strong>74.59%<\/strong><\/td>\n<td style=\"text-align: center;\" width=\"130\">96.57%<\/td>\n<td style=\"text-align: center;\">298.15<\/td>\n<td style=\"text-align: center;\">368.05<\/td>\n<\/tr>\n<tr>\n<td style=\"text-align: center;\" width=\"64\">B<\/td>\n<td style=\"text-align: center;\" width=\"90\">-0.984<\/td>\n<td style=\"text-align: center;\" width=\"82\">-0.141<\/td>\n<td style=\"text-align: center;\" width=\"89\">-9496.21<\/td>\n<td style=\"text-align: center;\" width=\"64\">-127.48<\/td>\n<td style=\"text-align: center;\" width=\"107\"><strong>85.67%<\/strong><\/td>\n<td style=\"text-align: center;\" width=\"130\">98.66%<\/td>\n<td style=\"text-align: center;\">287.03<\/td>\n<td style=\"text-align: center;\">378.64<\/td>\n<\/tr>\n<tr>\n<td style=\"text-align: center;\" width=\"64\">C<\/td>\n<td style=\"text-align: center;\" width=\"90\">-1.593<\/td>\n<td style=\"text-align: center;\" width=\"82\">-0.063<\/td>\n<td style=\"text-align: center;\" width=\"89\">-1972.426<\/td>\n<td style=\"text-align: center;\" width=\"64\">-6.406<\/td>\n<td style=\"text-align: center;\" width=\"107\"><strong>96.05%<\/strong><\/td>\n<td style=\"text-align: center;\" width=\"130\">99.68%<\/td>\n<td style=\"text-align: center;\">244.32<\/td>\n<td style=\"text-align: center;\">390.17<\/td>\n<\/tr>\n<tr>\n<td style=\"text-align: center;\" width=\"64\">D<\/td>\n<td style=\"text-align: center;\" width=\"90\">-1.679<\/td>\n<td style=\"text-align: center;\" width=\"82\">-0.043<\/td>\n<td style=\"text-align: center;\" width=\"89\">-21123.871<\/td>\n<td style=\"text-align: center;\" width=\"64\">-0.137<\/td>\n<td style=\"text-align: center;\" width=\"107\"><strong>97.44%<\/strong><\/td>\n<td style=\"text-align: center;\" width=\"130\">100.00%<\/td>\n<td style=\"text-align: center;\">239.29<\/td>\n<td style=\"text-align: center;\">393.24<\/td>\n<\/tr>\n<tr>\n<td style=\"text-align: center;\" width=\"64\">E<\/td>\n<td style=\"text-align: center;\" width=\"90\">-2.0<\/td>\n<td style=\"text-align: center;\" width=\"82\">-0.006<\/td>\n<td style=\"text-align: center;\" width=\"89\">-72974.359<\/td>\n<td style=\"text-align: center;\" width=\"64\">-0.006<\/td>\n<td style=\"text-align: center;\" width=\"107\"><strong>99.70%<\/strong><\/td>\n<td style=\"text-align: center;\" width=\"130\">100.00%<\/td>\n<td style=\"text-align: center;\">222.22<\/td>\n<td style=\"text-align: center;\">399.04<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>* Rounded up to 3 decimal places<\/p>\n<h3 class=\"alignnone\"><\/h3>\n<h3 class=\"alignnone\">Massive Productivity Gain &#8211; Results in 6 days<\/h3>\n<p>Although not all designs closed timing, this approach can significantly increase the FMax and improve the timing results in an automated fashion. The builds were accelerated through cloud computing (AWS) and the entire optimization process was driven by the InTime software. All five designs were optimized <span style=\"text-decoration: underline;\">at the same time<\/span> in only six days. Compared to solely focusing on iterative improvements, this represents a massive productivity gain for the entire organization.<\/p>\n<ul>\n<li><strong>Actual Wait Time: <\/strong>1.32 to\u00a06.24 days<\/li>\n<li><strong>Average Cloud Hours \/ Project: <\/strong>957 hours<\/li>\n<li><strong>Server Type: <\/strong>4 CPU, 31 Gb RAM<\/li>\n<\/ul>\n<h3>How to optimize routing-congested designs &#8211; InTime Timing Closure Methodology<\/h3>\n<p>Under the <a href=\"https:\/\/www.plunify.com\/en\/wp-content\/uploads\/sites\/8\/2018\/05\/InTime-Timing-Closure-Methodology-for-Vivado-WP04.pdf\" target=\"_blank\" rel=\"noopener\">InTime Timing Closure Methodology<\/a>, the build process is no longer a one-designer-to-one-machine operation. Instead, it is a systematic series of calculated steps done by one or many designers on multiple build machines. From the resulting analysis, InTime deduces and recommends sets of good build parameters aimed at improving design performance.<\/p>\n<h4>Explore Build Parameters<\/h4>\n<p>Routing congestion was a significant bottleneck for the five projects mentioned above. With this in mind, one approach was to explore relevant synthesis build parameters on all the designs. As this is a machine learning-driven software, multiple builds were necessary to generate data points for analysis. InTime is able to leverage on the compute resources in the cloud, running up to 200 servers concurrently for 12 hours, massively accelerating turnaround and time to results.<\/p>\n<p><img loading=\"lazy\" class=\"aligncenter wp-image-3479 size-full\" src=\"https:\/\/www.plunify.com\/en\/wp-content\/uploads\/sites\/8\/2018\/05\/learning_intime.png\" alt=\"InTime learning cycle - FPGA timing closure\" width=\"928\" height=\"561\" srcset=\"https:\/\/www.plunify.com\/en\/wp-content\/uploads\/sites\/8\/2018\/05\/learning_intime.png 928w, https:\/\/www.plunify.com\/en\/wp-content\/uploads\/sites\/8\/2018\/05\/learning_intime-300x181.png 300w, https:\/\/www.plunify.com\/en\/wp-content\/uploads\/sites\/8\/2018\/05\/learning_intime-768x464.png 768w\" sizes=\"(max-width: 928px) 100vw, 928px\" \/><\/p>\n<p><strong>Note<\/strong>: In Vivado, there are more than 30 build parameters, making up more than 1 billion different combinations. A classic brute-force approach will not work and will be terribly inefficient. At the other end of the spectrum, using a traditional iterative &#8220;change RTL, Build again and Repeat&#8221; is too time-consuming.<\/p>\n<p>Fortunately, cloud computing has commoditized compute power into CPU-hours, and through InTime&#8217;s disciplined process and methodology, InTime is able to converge onto good results efficiently. It takes <span style=\"text-decoration: underline;\">between\u00a026 to 414 builds<\/span> to achieve the results shown above. Comparing with more than 1 billion combinations, this is a tiny number. This is possible as InTime runs with a trained database that accumulates all the previous analysis from a diverse pool of designs.<\/p>\n<h4>Optimize Placement<\/h4>\n<p>Another key to optimizing a routing-congested design is to ensure good design placement. InTime has a &#8220;Placement Exploration&#8221; strategy akin to the old &#8220;Cost Tables&#8221; for ISE or Seed Sweep approach. This strategy is extremely effective for designs with negative slacks in the hundreds of picoseconds. It does not affect functionality and is safe and easy to use for timing closure.<\/p>\n<h3>Will this work for your design? Minimizing Risk and Increasing Chances of Meeting Timing<\/h3>\n<p>If you are uncertain about whether this approach will work for your design, you are more than welcome to <a href=\"https:\/\/www.plunify.com\/en\/free-evaluation\" target=\"_blank\" rel=\"noopener\"><strong>take a free evaluation of InTime<\/strong><\/a>.<\/p>\n<p>Please refer to the methodology guide section on results convergence. There are specific guidelines to check the likelihood of meeting timing for any design in general. Additionally, other tips such as how to <a href=\"https:\/\/support.plunify.com\/en\/2018\/03\/20\/how-to-reduce-your-build-time-by-50\/\" target=\"_blank\" rel=\"noopener\">reduce turnaround time<\/a> for your builds may be helpful.<\/p>\n<p>The other alternative is to consider\u00a0<a href=\"https:\/\/www.plunify.com\/en\/service\/\" target=\"_blank\" rel=\"noopener\">InTime Service<\/a>. InTime Service is a completely risk-free approach where Plunify helps you to ascertain if the design can be optimized to your requirements.<\/p>\n<p>For more information about InTime, please subscribe to our blog at\u00a0<a href=\"https:\/\/blog.plunify.com\">https:\/\/blog.plunify.com<\/a> or contact us at <a href=\"mailto:tellus@plunify.com\">tellus@plunify.com<\/a>.\u00a0 A copy of the methodology guide can be downloaded <a href=\"https:\/\/www.plunify.com\/en\/wp-content\/uploads\/sites\/8\/2018\/05\/InTime-Timing-Closure-Methodology-for-Vivado-WP04.pdf\">here<\/a>.[\/vc_column_text][\/vc_column][\/vc_row]<\/p>\n","protected":false},"excerpt":{"rendered":"<p>[vc_row row_type=&#8221;row&#8221; stretch_row_type=&#8221;no&#8221;][vc_column][vc_column_text]FPGAs are widely used in the Test and Measurement (T&amp;M) industry for their capabilities in high-speed signal processing, high precision data processing, and general design flexibility. As market demand for faster and more precise instrumentation increases, T&amp;M FPGA designs also become more complex and more challenging in terms of timing closure &#8211; directly [&hellip;]<\/p>\n","protected":false},"author":6,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"template-page-full-width.php","meta":{"spay_email":"","_links_to":"","_links_to_target":""},"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v17.0 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>FPGA Timing Closure for Congested Test &amp; Measurement Designs - A Machine Learning Solution &mdash; Plunify<\/title>\n<meta name=\"description\" content=\"Use machine learning in a new design optimization approach. Achieve timing closure on five large, routing-congested T&amp;M FPGA designs within a week.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.plunify.com\/en\/fpga-timing-closure-congested-test-measurement-designs-machine-learning\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"FPGA Timing Closure for Congested Test &amp; Measurement Designs - A Machine Learning Solution &mdash; Plunify\" \/>\n<meta property=\"og:description\" content=\"Use machine learning in a new design optimization approach. Achieve timing closure on five large, routing-congested T&amp;M FPGA designs within a week.\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.plunify.com\/en\/fpga-timing-closure-congested-test-measurement-designs-machine-learning\/\" \/>\n<meta property=\"og:site_name\" content=\"Plunify\" \/>\n<meta property=\"article:publisher\" content=\"https:\/\/www.facebook.com\/Plunify\" \/>\n<meta property=\"article:modified_time\" content=\"2019-02-08T04:15:46+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/www.plunify.com\/en\/wp-content\/uploads\/sites\/8\/2018\/05\/FMax_improvements.png\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:site\" content=\"@plunify\" \/>\n<meta name=\"twitter:label1\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data1\" content=\"4 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"Organization\",\"@id\":\"https:\/\/www.plunify.com\/en\/#organization\",\"name\":\"Plunify\",\"url\":\"https:\/\/www.plunify.com\/en\/\",\"sameAs\":[\"https:\/\/www.facebook.com\/Plunify\",\"https:\/\/www.linkedin.com\/company\/plunify\/\",\"https:\/\/www.youtube.com\/user\/Plunify\",\"https:\/\/twitter.com\/plunify\"],\"logo\":{\"@type\":\"ImageObject\",\"@id\":\"https:\/\/www.plunify.com\/en\/#logo\",\"inLanguage\":\"en-US\",\"url\":\"https:\/\/www.plunify.com\/en\/wp-content\/uploads\/sites\/8\/2017\/04\/logo-blueback.png\",\"contentUrl\":\"https:\/\/www.plunify.com\/en\/wp-content\/uploads\/sites\/8\/2017\/04\/logo-blueback.png\",\"width\":812,\"height\":346,\"caption\":\"Plunify\"},\"image\":{\"@id\":\"https:\/\/www.plunify.com\/en\/#logo\"}},{\"@type\":\"WebSite\",\"@id\":\"https:\/\/www.plunify.com\/en\/#website\",\"url\":\"https:\/\/www.plunify.com\/en\/\",\"name\":\"Plunify\",\"description\":\"Optimize your FPGA design\",\"publisher\":{\"@id\":\"https:\/\/www.plunify.com\/en\/#organization\"},\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\/\/www.plunify.com\/en\/?s={search_term_string}\"},\"query-input\":\"required name=search_term_string\"}],\"inLanguage\":\"en-US\"},{\"@type\":\"ImageObject\",\"@id\":\"https:\/\/www.plunify.com\/en\/fpga-timing-closure-congested-test-measurement-designs-machine-learning\/#primaryimage\",\"inLanguage\":\"en-US\",\"url\":\"https:\/\/www.plunify.com\/en\/wp-content\/uploads\/sites\/8\/2018\/05\/FMax_improvements.png\",\"contentUrl\":\"https:\/\/www.plunify.com\/en\/wp-content\/uploads\/sites\/8\/2018\/05\/FMax_improvements.png\",\"width\":797,\"height\":461},{\"@type\":\"WebPage\",\"@id\":\"https:\/\/www.plunify.com\/en\/fpga-timing-closure-congested-test-measurement-designs-machine-learning\/#webpage\",\"url\":\"https:\/\/www.plunify.com\/en\/fpga-timing-closure-congested-test-measurement-designs-machine-learning\/\",\"name\":\"FPGA Timing Closure for Congested Test &amp; Measurement Designs - A Machine Learning Solution &mdash; Plunify\",\"isPartOf\":{\"@id\":\"https:\/\/www.plunify.com\/en\/#website\"},\"primaryImageOfPage\":{\"@id\":\"https:\/\/www.plunify.com\/en\/fpga-timing-closure-congested-test-measurement-designs-machine-learning\/#primaryimage\"},\"datePublished\":\"2018-05-10T09:42:01+00:00\",\"dateModified\":\"2019-02-08T04:15:46+00:00\",\"description\":\"Use machine learning in a new design optimization approach. Achieve timing closure on five large, routing-congested T&M FPGA designs within a week.\",\"breadcrumb\":{\"@id\":\"https:\/\/www.plunify.com\/en\/fpga-timing-closure-congested-test-measurement-designs-machine-learning\/#breadcrumb\"},\"inLanguage\":\"en-US\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\/\/www.plunify.com\/en\/fpga-timing-closure-congested-test-measurement-designs-machine-learning\/\"]}]},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\/\/www.plunify.com\/en\/fpga-timing-closure-congested-test-measurement-designs-machine-learning\/#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"Home\",\"item\":\"https:\/\/www.plunify.com\/en\/\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"FPGA Timing Closure for Congested Test &amp; Measurement Designs &#8211; A Machine Learning Solution\"}]}]}<\/script>\n<!-- \/ Yoast SEO plugin. -->","yoast_head_json":{"title":"FPGA Timing Closure for Congested Test &amp; Measurement Designs - A Machine Learning Solution &mdash; Plunify","description":"Use machine learning in a new design optimization approach. Achieve timing closure on five large, routing-congested T&M FPGA designs within a week.","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/www.plunify.com\/en\/fpga-timing-closure-congested-test-measurement-designs-machine-learning\/","og_locale":"en_US","og_type":"article","og_title":"FPGA Timing Closure for Congested Test &amp; Measurement Designs - A Machine Learning Solution &mdash; Plunify","og_description":"Use machine learning in a new design optimization approach. Achieve timing closure on five large, routing-congested T&M FPGA designs within a week.","og_url":"https:\/\/www.plunify.com\/en\/fpga-timing-closure-congested-test-measurement-designs-machine-learning\/","og_site_name":"Plunify","article_publisher":"https:\/\/www.facebook.com\/Plunify","article_modified_time":"2019-02-08T04:15:46+00:00","og_image":[{"url":"https:\/\/www.plunify.com\/en\/wp-content\/uploads\/sites\/8\/2018\/05\/FMax_improvements.png"}],"twitter_card":"summary_large_image","twitter_site":"@plunify","twitter_misc":{"Est. reading time":"4 minutes"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"Organization","@id":"https:\/\/www.plunify.com\/en\/#organization","name":"Plunify","url":"https:\/\/www.plunify.com\/en\/","sameAs":["https:\/\/www.facebook.com\/Plunify","https:\/\/www.linkedin.com\/company\/plunify\/","https:\/\/www.youtube.com\/user\/Plunify","https:\/\/twitter.com\/plunify"],"logo":{"@type":"ImageObject","@id":"https:\/\/www.plunify.com\/en\/#logo","inLanguage":"en-US","url":"https:\/\/www.plunify.com\/en\/wp-content\/uploads\/sites\/8\/2017\/04\/logo-blueback.png","contentUrl":"https:\/\/www.plunify.com\/en\/wp-content\/uploads\/sites\/8\/2017\/04\/logo-blueback.png","width":812,"height":346,"caption":"Plunify"},"image":{"@id":"https:\/\/www.plunify.com\/en\/#logo"}},{"@type":"WebSite","@id":"https:\/\/www.plunify.com\/en\/#website","url":"https:\/\/www.plunify.com\/en\/","name":"Plunify","description":"Optimize your FPGA design","publisher":{"@id":"https:\/\/www.plunify.com\/en\/#organization"},"potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/www.plunify.com\/en\/?s={search_term_string}"},"query-input":"required name=search_term_string"}],"inLanguage":"en-US"},{"@type":"ImageObject","@id":"https:\/\/www.plunify.com\/en\/fpga-timing-closure-congested-test-measurement-designs-machine-learning\/#primaryimage","inLanguage":"en-US","url":"https:\/\/www.plunify.com\/en\/wp-content\/uploads\/sites\/8\/2018\/05\/FMax_improvements.png","contentUrl":"https:\/\/www.plunify.com\/en\/wp-content\/uploads\/sites\/8\/2018\/05\/FMax_improvements.png","width":797,"height":461},{"@type":"WebPage","@id":"https:\/\/www.plunify.com\/en\/fpga-timing-closure-congested-test-measurement-designs-machine-learning\/#webpage","url":"https:\/\/www.plunify.com\/en\/fpga-timing-closure-congested-test-measurement-designs-machine-learning\/","name":"FPGA Timing Closure for Congested Test &amp; Measurement Designs - A Machine Learning Solution &mdash; Plunify","isPartOf":{"@id":"https:\/\/www.plunify.com\/en\/#website"},"primaryImageOfPage":{"@id":"https:\/\/www.plunify.com\/en\/fpga-timing-closure-congested-test-measurement-designs-machine-learning\/#primaryimage"},"datePublished":"2018-05-10T09:42:01+00:00","dateModified":"2019-02-08T04:15:46+00:00","description":"Use machine learning in a new design optimization approach. Achieve timing closure on five large, routing-congested T&M FPGA designs within a week.","breadcrumb":{"@id":"https:\/\/www.plunify.com\/en\/fpga-timing-closure-congested-test-measurement-designs-machine-learning\/#breadcrumb"},"inLanguage":"en-US","potentialAction":[{"@type":"ReadAction","target":["https:\/\/www.plunify.com\/en\/fpga-timing-closure-congested-test-measurement-designs-machine-learning\/"]}]},{"@type":"BreadcrumbList","@id":"https:\/\/www.plunify.com\/en\/fpga-timing-closure-congested-test-measurement-designs-machine-learning\/#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"Home","item":"https:\/\/www.plunify.com\/en\/"},{"@type":"ListItem","position":2,"name":"FPGA Timing Closure for Congested Test &amp; Measurement Designs &#8211; A Machine Learning Solution"}]}]}},"_links":{"self":[{"href":"https:\/\/www.plunify.com\/en\/wp-json\/wp\/v2\/pages\/3469"}],"collection":[{"href":"https:\/\/www.plunify.com\/en\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.plunify.com\/en\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.plunify.com\/en\/wp-json\/wp\/v2\/users\/6"}],"replies":[{"embeddable":true,"href":"https:\/\/www.plunify.com\/en\/wp-json\/wp\/v2\/comments?post=3469"}],"version-history":[{"count":66,"href":"https:\/\/www.plunify.com\/en\/wp-json\/wp\/v2\/pages\/3469\/revisions"}],"predecessor-version":[{"id":4558,"href":"https:\/\/www.plunify.com\/en\/wp-json\/wp\/v2\/pages\/3469\/revisions\/4558"}],"wp:attachment":[{"href":"https:\/\/www.plunify.com\/en\/wp-json\/wp\/v2\/media?parent=3469"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}