{"id":1275,"date":"2017-01-18T14:54:11","date_gmt":"2017-01-18T14:54:11","guid":{"rendered":"http:\/\/www.plunify.com\/en\/?page_id=1275"},"modified":"2018-05-18T10:32:57","modified_gmt":"2018-05-18T02:32:57","slug":"publications","status":"publish","type":"page","link":"https:\/\/www.plunify.com\/en\/publications\/","title":{"rendered":"Publications"},"content":{"rendered":"

[vc_row row_type=”row” stretch_row_type=”no” css=”.vc_custom_1484622607279{margin-top: 20px !important;}”][vc_column][vc_column_text css=”.vc_custom_1497432667111{padding-top: 10px !important;}”]<\/p>\n

Publications<\/h2>\n

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Many of our research papers are published on FPGA conferences and are free for download. Contact\u00a0us<\/a> if you want more information.<\/p>\n

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\"tech1\"
\nBoosting Convergence of Timing Closure using Feature Selection in a Learning-driven Approach<\/strong><\/h4>\n

Event: 2016 26th International Conference on Field Programmable Logic and Applications (FPL)<\/span><\/em><\/p>\n

Machine Learning approaches for automated selection of FPGA CAD tool parameters have been demonstrated to be useful for timing closure of FPGA designs [3], [4]. This is achieved by running the CAD tool multiple times with small variations in the the CAD parameter values. The timing slack from each run is recorded into a database along with all input parameter selections to help train a classifier.\u00a0By progressively running more instances of the tool, we can help drive the CAD tool towards timing convergence…[\/vc_column_text][vc_btn title=”READ MORE” color=”sky” size=”sm” align=”right” i_icon_fontawesome=”fa fa-download” add_icon=”true” link=”url:https%3A%2F%2Fwww.plunify.com%2Fen%2Fwp-content%2Fuploads%2Fsites%2F8%2F2017%2F01%2Fintime_fpl2016.pdf|title:Download%20PDF|target:%20_blank|” custom_onclick=”true” custom_onclick_code=”ga(‘send’, { hitType: ‘event’, eventCategory: ‘File’, eventAction: ‘download’, eventLabel: ‘Publication_Boosting_Convergence’ });”][vc_empty_space height=”20px”][vc_row_inner][vc_column_inner][vc_column_text]<\/p>\n

\"tech2\"<\/span>Improving Classification Accuracy of a Machine Learning approach for FPGA Timing Closure<\/strong><\/h4>\n

Event: 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)<\/span><\/em><\/p>\n

We can use Cloud Computing and Machine Learning to help deliver timing closure of FPGA designs using InTime [2], [3]. This approach requires no modification to the input RTL and relies exclusively on manipulating the CAD tool parameters that drive the optimization heuristics. By running multiple combinations of the parameters in parallel, we learn from results and identify which parameters\u00a0caused an improvement in the final results…[\/vc_column_text][vc_btn title=”READ MORE” color=”sky” size=”sm” align=”right” i_icon_fontawesome=”fa fa-download” add_icon=”true” link=”url:https%3A%2F%2Fwww.plunify.com%2Fen%2Fwp-content%2Fuploads%2Fsites%2F8%2F2017%2F01%2Fml-classifiers_fccm2016.pdf|title:Download%20PDF|target:%20_blank|” custom_onclick=”true” custom_onclick_code=”ga(‘send’, { hitType: ‘event’, eventCategory: ‘File’, eventAction: ‘download’, eventLabel: ‘Publication_Improving_Classification’ });”][\/vc_column_inner][\/vc_row_inner][vc_empty_space height=”20px”][vc_row_inner][vc_column_inner][vc_column_text]<\/p>\n

\"tech3\"<\/span>Case for Design-Specific Machine Learning in Timing Closure of FPGA Designs<\/strong><\/h4>\n

Event: FPGA ’16 Proceedings of the 2016 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays<\/span><\/em><\/p>\n

We can achieve reliable timing closure of FPGA designs us ing machine learning heuristics to generate input parameter settings for FPGA CAD tools. This is enabled by running multiple instances of CAD tool with different sets of these input parameters and logging of resulting timing slack values into a database. We incrementally build this database and run learning routines to develop suitable classier models\u00a0that correlate input parameter combinations to resulting slack. As each CAD run in independent, we can trivially parallelize our exploration…[\/vc_column_text][vc_btn title=”READ MORE” color=”sky” size=”sm” align=”right” i_icon_fontawesome=”fa fa-download” add_icon=”true” link=”url:https%3A%2F%2Fwww.plunify.com%2Fen%2Fwp-content%2Fuploads%2Fsites%2F8%2F2017%2F01%2Fml-case_fpga2016.pdf|title:Download%20PDF|target:%20_blank|” custom_onclick=”true” custom_onclick_code=”ga(‘send’, { hitType: ‘event’, eventCategory: ‘File’, eventAction: ‘download’, eventLabel: ‘Publication_Specific_MachineLearning’ });”][\/vc_column_inner][\/vc_row_inner][vc_empty_space height=”20px”][vc_row_inner][vc_column_inner][vc_column_text]<\/p>\n

\"tech4\"<\/span>Driving Timing Convergence of FPGA Designs through Machine Learning and Cloud Computing<\/strong><\/h4>\n

Event: Field-Programmable Custom Computing Machines (FCCM), 2015 IEEE 23rd Annual International Symposium on 2-6 May 2015<\/em><\/span><\/p>\n

Machine learning and cloud computing techniques can help accelerate timing closure for FPGA designs without any modification to original RTL code. RTL is generally frozen closer to system delivery target to avoid injecting new unforeseen bugs or significantly affecting design characteristics.\u00a0In these circumstances, developers trying to close timing are either at the mercy of random trials through placement seed exploration…[\/vc_column_text][vc_btn title=”READ MORE” color=”sky” size=”sm” align=”right” i_icon_fontawesome=”fa fa-download” add_icon=”true” link=”url:https%3A%2F%2Fwww.plunify.com%2Fen%2Fwp-content%2Fuploads%2Fsites%2F8%2F2017%2F01%2Fintime_fccm2015.pdf|title:Download%20PDF|target:%20_blank|” custom_onclick=”true” custom_onclick_code=”ga(‘send’, { hitType: ‘event’, eventCategory: ‘File’, eventAction: ‘download’, eventLabel: ‘Publication_Driving_Timing’ });”][\/vc_column_inner][\/vc_row_inner][vc_empty_space height=”20px”][vc_row_inner][vc_column_inner][vc_column_text]<\/p>\n

\"tech5\"<\/span>InTime: A Machine Learning Approach for Efficient Selection of FPGA CAD Tool Parameters<\/strong><\/h4>\n

Event: FPGA ’15 Proceedings of the 2015 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays<\/span><\/em><\/p>\n

FPGA CAD tool parameters controlling synthesis optimizations, place and route effort, mapping criteria along with user-supplied physical constraints can affect timing results of the circuit by as much as 70% without any change in original source code. A correct selection of these parameters across…[\/vc_column_text][vc_btn title=”READ MORE” color=”sky” size=”sm” align=”right” i_icon_fontawesome=”fa fa-download” add_icon=”true” link=”url:https%3A%2F%2Fwww.plunify.com%2Fen%2Fwp-content%2Fuploads%2Fsites%2F8%2F2017%2F01%2Fintime_fpga2015.pdf|title:Download%20PDF|target:%20_blank|” custom_onclick=”true” custom_onclick_code=”ga(‘send’, { hitType: ‘event’, eventCategory: ‘File’, eventAction: ‘download’, eventLabel: ‘Publication_MachineLearning_Approach’ });”][\/vc_column_inner][\/vc_row_inner][vc_empty_space height=”20px”][\/vc_column][\/vc_row]<\/p>\n","protected":false},"excerpt":{"rendered":"

[vc_row row_type=”row” stretch_row_type=”no” css=”.vc_custom_1484622607279{margin-top: 20px !important;}”][vc_column][vc_column_text css=”.vc_custom_1497432667111{padding-top: 10px !important;}”] Publications [\/vc_column_text][vc_column_text css=”.vc_custom_1503480559650{padding-top: 0px !important;}”] Many of our research papers are published on FPGA conferences and are free for download. Contact\u00a0us if you want more information. [\/vc_column_text][\/vc_column][\/vc_row][vc_row row_type=”row” stretch_row_type=”no”][vc_column][vc_column_text] Boosting Convergence of Timing Closure using Feature Selection in a Learning-driven Approach Event: 2016 26th International Conference […]<\/p>\n","protected":false},"author":12,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"template-page-full-width-vc.php","meta":{"spay_email":"","_links_to":"","_links_to_target":""},"yoast_head":"\nPublications — Plunify<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.plunify.com\/en\/publications\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Publications — Plunify\" \/>\n<meta property=\"og:description\" content=\"[vc_row row_type=”row” stretch_row_type=”no” css=”.vc_custom_1484622607279{margin-top: 20px !important;}”][vc_column][vc_column_text css=”.vc_custom_1497432667111{padding-top: 10px !important;}”] Publications [\/vc_column_text][vc_column_text css=”.vc_custom_1503480559650{padding-top: 0px !important;}”] Many of our research papers are published on FPGA conferences and are free for download. Contact\u00a0us if you want more information. [\/vc_column_text][\/vc_column][\/vc_row][vc_row row_type=”row” stretch_row_type=”no”][vc_column][vc_column_text] Boosting Convergence of Timing Closure using Feature Selection in a Learning-driven Approach Event: 2016 26th International Conference […]\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.plunify.com\/en\/publications\/\" \/>\n<meta property=\"og:site_name\" content=\"Plunify\" \/>\n<meta property=\"article:publisher\" content=\"https:\/\/www.facebook.com\/Plunify\" \/>\n<meta property=\"article:modified_time\" content=\"2018-05-18T02:32:57+00:00\" \/>\n<meta property=\"og:image\" content=\"http:\/\/www.plunify.com\/en\/wp-content\/uploads\/sites\/8\/2017\/01\/tech1.jpg\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:site\" content=\"@plunify\" \/>\n<meta name=\"twitter:label1\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data1\" content=\"5 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"Organization\",\"@id\":\"https:\/\/www.plunify.com\/en\/#organization\",\"name\":\"Plunify\",\"url\":\"https:\/\/www.plunify.com\/en\/\",\"sameAs\":[\"https:\/\/www.facebook.com\/Plunify\",\"https:\/\/www.linkedin.com\/company\/plunify\/\",\"https:\/\/www.youtube.com\/user\/Plunify\",\"https:\/\/twitter.com\/plunify\"],\"logo\":{\"@type\":\"ImageObject\",\"@id\":\"https:\/\/www.plunify.com\/en\/#logo\",\"inLanguage\":\"en-US\",\"url\":\"https:\/\/www.plunify.com\/en\/wp-content\/uploads\/sites\/8\/2017\/04\/logo-blueback.png\",\"contentUrl\":\"https:\/\/www.plunify.com\/en\/wp-content\/uploads\/sites\/8\/2017\/04\/logo-blueback.png\",\"width\":812,\"height\":346,\"caption\":\"Plunify\"},\"image\":{\"@id\":\"https:\/\/www.plunify.com\/en\/#logo\"}},{\"@type\":\"WebSite\",\"@id\":\"https:\/\/www.plunify.com\/en\/#website\",\"url\":\"https:\/\/www.plunify.com\/en\/\",\"name\":\"Plunify\",\"description\":\"Optimize your FPGA design\",\"publisher\":{\"@id\":\"https:\/\/www.plunify.com\/en\/#organization\"},\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\/\/www.plunify.com\/en\/?s={search_term_string}\"},\"query-input\":\"required name=search_term_string\"}],\"inLanguage\":\"en-US\"},{\"@type\":\"ImageObject\",\"@id\":\"https:\/\/www.plunify.com\/en\/publications\/#primaryimage\",\"inLanguage\":\"en-US\",\"url\":\"http:\/\/www.plunify.com\/en\/wp-content\/uploads\/sites\/8\/2017\/01\/tech1.jpg\",\"contentUrl\":\"http:\/\/www.plunify.com\/en\/wp-content\/uploads\/sites\/8\/2017\/01\/tech1.jpg\"},{\"@type\":\"WebPage\",\"@id\":\"https:\/\/www.plunify.com\/en\/publications\/#webpage\",\"url\":\"https:\/\/www.plunify.com\/en\/publications\/\",\"name\":\"Publications — Plunify\",\"isPartOf\":{\"@id\":\"https:\/\/www.plunify.com\/en\/#website\"},\"primaryImageOfPage\":{\"@id\":\"https:\/\/www.plunify.com\/en\/publications\/#primaryimage\"},\"datePublished\":\"2017-01-18T14:54:11+00:00\",\"dateModified\":\"2018-05-18T02:32:57+00:00\",\"breadcrumb\":{\"@id\":\"https:\/\/www.plunify.com\/en\/publications\/#breadcrumb\"},\"inLanguage\":\"en-US\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\/\/www.plunify.com\/en\/publications\/\"]}]},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\/\/www.plunify.com\/en\/publications\/#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"Home\",\"item\":\"https:\/\/www.plunify.com\/en\/\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"Publications\"}]}]}<\/script>\n<!-- \/ Yoast SEO plugin. -->","yoast_head_json":{"title":"Publications — Plunify","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/www.plunify.com\/en\/publications\/","og_locale":"en_US","og_type":"article","og_title":"Publications — Plunify","og_description":"[vc_row row_type=”row” stretch_row_type=”no” css=”.vc_custom_1484622607279{margin-top: 20px !important;}”][vc_column][vc_column_text css=”.vc_custom_1497432667111{padding-top: 10px !important;}”] Publications [\/vc_column_text][vc_column_text css=”.vc_custom_1503480559650{padding-top: 0px !important;}”] Many of our research papers are published on FPGA conferences and are free for download. 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