{"id":2311,"date":"2017-06-08T16:11:42","date_gmt":"2017-06-08T08:11:42","guid":{"rendered":"http:\/\/www.plunify.com\/cn\/?page_id=2311"},"modified":"2018-02-07T09:48:49","modified_gmt":"2018-02-07T01:48:49","slug":"pr20170606","status":"publish","type":"page","link":"https:\/\/www.plunify.com\/cn\/pr20170606\/","title":{"rendered":"Press Releases, 6 Jun 2017"},"content":{"rendered":"

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Press Releases<\/h2>\n

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Plunify Introduces Software to Minimize, Eliminate Performance Errors in FPGA Designs<\/h1>\n

First-Time DAC Exhibitor Will Demonstrate Portfolio of Machine Learning-Based Tools.<\/strong><\/p>\n

SINGAPORE–(Marketwired – Jun 6, 2017)<\/strong> – Plunify\u00ae<\/a>, supplier of field programmable gate array (FPGA) timing and performance software based on machine learning techniques, today introduced Kabuto\u2122 to minimize and eliminate performance errors.<\/p>\n

Kabuto joins Plunify’s InTime\u2122 for time closure and performance optimization to solve critical design problems for a variety of markets, including data center, advanced driver assistance systems and high-frequency trading. “Our machine learning features for timing closure and optimizing FPGA designs enables our users to outperform their competitors,” remarks Harnhua Ng, Plunify’s chief executive officer and co-founder.<\/p>\n

Plunify will exhibit at the Design Automation Conference (DAC) in Booth #1631 June 19-21 from10 a.m. until 6 p.m. at the Austin Convention Center in Austin, Texas. It will offer continuous demonstrations of its complete product portfolio.<\/p>\n

Introducing Kabuto for fixing RTL Code Performance
\n<\/strong>Kabuto, the Japanese term for “helmet,” protects FPGA designs from performance errors by recommending register transfer level (RTL) code fixes based on timing path and RTL code analysis. It reads critical-path information and pinpoints corresponding source code segments, analyzes them and then proposes RTL fixes.<\/p>\n

For instance, Kabuto can identify the need to pipeline a design, suggest the exact lines of code to be modified and ensure that dependencies are checked properly. Unlike linting tools, Kabuto recommends fixes for bad timing paths at the register transfer level.<\/p>\n

Added Capabilities to InTime
\n<\/strong>As FPGAs and design flows become more complex, the number and difficulty of critical timing and performance issues increase exponentially. InTime timing closure and performance optimization addresses these challenges using a unique data-driven approach and helps engineering groups achieve their design timing goals. It learns and infers the best tool parameters, such as synthesis options, place & route options and placement locations, for a design. InTime uses statistical modeling and machine learning capabilities to draw insights from the data to improve quality of results.<\/p>\n

The latest version offers improved timing control and performance capabilities. An Auto Placement feature now supports Quartus Prime Pro 17.0, Quartus 17.0, Vivado 2017.1. InTime runs fully automated on the user’s servers or in a cloud computing environment.<\/p>\n

The latest capabilities enable customers to build their own proprietary design database, ensuring that the more an engineering group uses InTime, the smarter the group’s learning database becomes, further accelerating the time to design closure.<\/p>\n

While InTime is used primarily for timing closure, Plunify’s algorithms can be applied to critical variables like power and area as well.<\/p>\n

Availability and Pricing<\/strong><\/p>\n