{"id":1542,"date":"2017-02-07T07:27:52","date_gmt":"2017-02-07T07:27:52","guid":{"rendered":"http:\/\/www.plunify.com\/cn\/?page_id=1542"},"modified":"2017-02-09T00:55:57","modified_gmt":"2017-02-09T00:55:57","slug":"pr20111213","status":"publish","type":"page","link":"https:\/\/www.plunify.com\/cn\/pr20111213\/","title":{"rendered":"Press Releases, 13 Dec 2011"},"content":{"rendered":"<p>[vc_row row_type=&#8221;row&#8221; stretch_row_type=&#8221;no&#8221; css=&#8221;.vc_custom_1484623020079{margin-top: 20px !important;}&#8221;][vc_column][vc_column_text css=&#8221;.vc_custom_1486601759899{padding-top: 50px !important;}&#8221;]<\/p>\n<h2 style=\"text-align: center\">Press Releases<\/h2>\n<p>[\/vc_column_text][\/vc_column][\/vc_row][vc_row row_type=&#8221;row&#8221; stretch_row_type=&#8221;no&#8221;][vc_column][vc_column_text]<\/p>\n<h1>Plunify releases desktop plugin for rapid and scalable cloud-based fpga design and timing closure<\/h1>\n<p>&nbsp;<\/p>\n<p align=\"left\"><strong>Automated Timing Closure and Design Compilation Using Major FPGA Vendor Tools<\/strong><\/p>\n<p><strong>Singapore, December 13, 2011<\/strong> \u2013 Accelerating time-to-market and lowering development costs for FPGA designers, <a href=\"http:\/\/www.plunify.com\/\">Plunify Pte Ltd<\/a> today announced the release of FPGAAccel\u2122 Client 1.0, a desktop plugin designed to enable cloud-based FPGA design with little or no disruption to existing workflows. \u00a0Hardware developers can immediately use the plugin to offload CPU- and memory-intensive tasks to Plunify\u2019s managed cloud and run them in parallel, potentially reducing days of effort into a few hours.<\/p>\n<p>Integrated directly with major FPGA software tools, the FPGAAccel client does not require a steep learning curve and needs only a working Internet connection.\u00a0 Tasks like synthesis and place-and-route can be selectively sent for remote processing.\u00a0 Because local resources are freed up, the FPGAAccel client can also be used when traveling or at a remote site.\u00a0 Results are made available via both command-line and Web-based interfaces.<\/p>\n<p>Focusing on timing closure as a particularly resource- and time-consuming process, Plunify has implemented algorithms into the FPGAAccel client to help users achieve timing closure as quickly as possible.\u00a0 According to Harnhua Ng, Director of Engineering at Plunify, &#8220;According to our users, being able to run tasks in parallel with a simple script command has been a tremendous help, especially for timing closure. With the FPGAAccel client, one can start a series of builds before leaving the office and get all the results the following morning.&#8221;<\/p>\n<p>The FPGAAccel client supports major FPGA software tools on Windows and Linux platforms, and is available as a free download at <a href=\"http:\/\/www.plunify.com\/cn\/portal.php\">http:\/\/www.plunify.com\/cn\/portal.php<\/a> .<\/p>\n<p>For more information, visit <a href=\"http:\/\/www.plunify.com\/\">www.plunify.com<\/a>.\u00a0 A case study on Plunify\u2019s scalable, distributed approach to attempting timing closure using cloud computing resources can be found at<a href=\"http:\/\/www.plunify.com\/downloads\/Plunify_Case_Study_OR1200.pdf\">http:\/\/www.plunify.com\/downloads\/Plunify_Case_Study_OR1200.pdf<\/a>.<\/p>\n<p><strong>About Plunify Pte.Ltd.<\/strong><\/p>\n<p>Plunify\u00ae cloud computing solutions enable semiconductor chip designers to shorten product time-to-market and reduce development costs with no disruption to existing workflows. For more on \u201cAccelerating Time-to-Market with Cloud Computing\u201d, and to find out more about Plunify\u2019s EDAxtend platform and FPGAAccel products, visit <a href=\"http:\/\/www.plunify.com\/\">http:\/\/www.plunify.com<\/a>. Follow Plunify via <a href=\"http:\/\/www.facebook.com\/pages\/Singapore\/Plunify\/91188649764\">Facebook<\/a>, <a href=\"http:\/\/www.twitter.com\/plunify\">Twitter<\/a>and <a href=\"http:\/\/plunify.blogspot.com\/\">Blogger<\/a>. Plunify, Plunify EDAxtend and Plunify FPGAAccel are trademarks of Plunify Pte Ltd. All others are trademarks or registered trademarks of their respective owners.<\/p>\n<p><strong>Media Contact:<\/strong><\/p>\n<p>Harnhua NG<br \/>\nPlunify Pte Ltd<br \/>\nmedia@plunify.com[\/vc_column_text][\/vc_column][\/vc_row]<\/p>\n","protected":false},"excerpt":{"rendered":"<p>[vc_row row_type=&#8221;row&#8221; stretch_row_type=&#8221;no&#8221; css=&#8221;.vc_custom_1484623020079{margin-top: 20px !important;}&#8221;][vc_column][vc_column_text css=&#8221;.vc_custom_1486601759899{padding-top: 50px !important;}&#8221;] Press Releases [\/vc_column_text][\/vc_column][\/vc_row][vc_row row_type=&#8221;row&#8221; stretch_row_type=&#8221;no&#8221;][vc_column][vc_column_text] Plunify releases desktop plugin for rapid and scalable cloud-based fpga design and timing closure &nbsp; Automated Timing Closure and Design Compilation Using Major FPGA Vendor Tools Singapore, December 13, 2011 \u2013 Accelerating time-to-market and lowering development costs for FPGA designers, Plunify [&hellip;]<\/p>\n","protected":false},"author":6,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"template-page-full-width-vc.php","meta":{"_links_to":"","_links_to_target":""},"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v17.0 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Press Releases, 13 Dec 2011 - Plunify \u6d66\u5229\u4e30<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.plunify.com\/cn\/pr20111213\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Press Releases, 13 Dec 2011 - Plunify \u6d66\u5229\u4e30\" \/>\n<meta property=\"og:description\" content=\"[vc_row row_type=&#8221;row&#8221; stretch_row_type=&#8221;no&#8221; css=&#8221;.vc_custom_1484623020079{margin-top: 20px !important;}&#8221;][vc_column][vc_column_text css=&#8221;.vc_custom_1486601759899{padding-top: 50px !important;}&#8221;] Press Releases [\/vc_column_text][\/vc_column][\/vc_row][vc_row row_type=&#8221;row&#8221; stretch_row_type=&#8221;no&#8221;][vc_column][vc_column_text] Plunify releases desktop plugin for rapid and scalable cloud-based fpga design and timing closure &nbsp; Automated Timing Closure and Design Compilation Using Major FPGA Vendor Tools Singapore, December 13, 2011 \u2013 Accelerating time-to-market and lowering development costs for FPGA designers, Plunify [&hellip;]\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.plunify.com\/cn\/pr20111213\/\" \/>\n<meta property=\"og:site_name\" content=\"Plunify \u6d66\u5229\u4e30\" \/>\n<meta property=\"article:publisher\" content=\"https:\/\/www.facebook.com\/Plunify\" \/>\n<meta property=\"article:modified_time\" content=\"2017-02-09T00:55:57+00:00\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:site\" content=\"@plunify\" \/>\n<meta name=\"twitter:label1\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data1\" content=\"2 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"Organization\",\"@id\":\"https:\/\/www.plunify.com\/cn\/#organization\",\"name\":\"Plunify\",\"url\":\"https:\/\/www.plunify.com\/cn\/\",\"sameAs\":[\"https:\/\/www.facebook.com\/Plunify\",\"https:\/\/www.linkedin.com\/company\/611504\/\",\"https:\/\/www.youtube.com\/user\/Plunify\/\",\"https:\/\/twitter.com\/plunify\"],\"logo\":{\"@type\":\"ImageObject\",\"@id\":\"https:\/\/www.plunify.com\/cn\/#logo\",\"inLanguage\":\"en-US\",\"url\":\"https:\/\/www.plunify.com\/cn\/wp-content\/uploads\/sites\/10\/2017\/04\/logo-blueback.png\",\"contentUrl\":\"https:\/\/www.plunify.com\/cn\/wp-content\/uploads\/sites\/10\/2017\/04\/logo-blueback.png\",\"width\":812,\"height\":346,\"caption\":\"Plunify\"},\"image\":{\"@id\":\"https:\/\/www.plunify.com\/cn\/#logo\"}},{\"@type\":\"WebSite\",\"@id\":\"https:\/\/www.plunify.com\/cn\/#website\",\"url\":\"https:\/\/www.plunify.com\/cn\/\",\"name\":\"Plunify \\u6d66\\u5229\\u4e30\",\"description\":\"\\u4f18\\u5316\\u60a8\\u7684 FPGA \\u8bbe\\u8ba1\",\"publisher\":{\"@id\":\"https:\/\/www.plunify.com\/cn\/#organization\"},\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\/\/www.plunify.com\/cn\/?s={search_term_string}\"},\"query-input\":\"required name=search_term_string\"}],\"inLanguage\":\"en-US\"},{\"@type\":\"WebPage\",\"@id\":\"https:\/\/www.plunify.com\/cn\/pr20111213\/#webpage\",\"url\":\"https:\/\/www.plunify.com\/cn\/pr20111213\/\",\"name\":\"Press Releases, 13 Dec 2011 - Plunify \\u6d66\\u5229\\u4e30\",\"isPartOf\":{\"@id\":\"https:\/\/www.plunify.com\/cn\/#website\"},\"datePublished\":\"2017-02-07T07:27:52+00:00\",\"dateModified\":\"2017-02-09T00:55:57+00:00\",\"breadcrumb\":{\"@id\":\"https:\/\/www.plunify.com\/cn\/pr20111213\/#breadcrumb\"},\"inLanguage\":\"en-US\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\/\/www.plunify.com\/cn\/pr20111213\/\"]}]},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\/\/www.plunify.com\/cn\/pr20111213\/#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"Home\",\"item\":\"https:\/\/www.plunify.com\/cn\/\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"Press Releases, 13 Dec 2011\"}]}]}<\/script>\n<!-- \/ Yoast SEO plugin. -->","yoast_head_json":{"title":"Press Releases, 13 Dec 2011 - Plunify \u6d66\u5229\u4e30","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/www.plunify.com\/cn\/pr20111213\/","og_locale":"en_US","og_type":"article","og_title":"Press Releases, 13 Dec 2011 - Plunify \u6d66\u5229\u4e30","og_description":"[vc_row row_type=&#8221;row&#8221; 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