{"id":1521,"date":"2017-02-07T06:01:38","date_gmt":"2017-02-07T06:01:38","guid":{"rendered":"http:\/\/www.plunify.com\/cn\/?page_id=1521"},"modified":"2017-02-09T01:03:16","modified_gmt":"2017-02-09T01:03:16","slug":"pr20141112","status":"publish","type":"page","link":"https:\/\/www.plunify.com\/cn\/pr20141112\/","title":{"rendered":"Press Releases, 12 Nov 2014"},"content":{"rendered":"<p>[vc_row row_type=&#8221;row&#8221; stretch_row_type=&#8221;no&#8221; css=&#8221;.vc_custom_1484623020079{margin-top: 20px !important;}&#8221;][vc_column][vc_column_text css=&#8221;.vc_custom_1486602199294{padding-top: 50px !important;}&#8221;]<\/p>\n<h2 style=\"text-align: center\">Press Releases<\/h2>\n<p>[\/vc_column_text][\/vc_column][\/vc_row][vc_row row_type=&#8221;row&#8221; stretch_row_type=&#8221;no&#8221;][vc_column][vc_column_text]<\/p>\n<h1>Plunify\u2019s InTime Design Optimization Software Supports Altera FPGAs and SoCs<\/h1>\n<p>&nbsp;<\/p>\n<p align=\"left\"><strong>InTime Software Uses Advanced Computing Techniques to Accelerate Time to Production<\/strong><\/p>\n<p><strong>LOS ALTOS, CA&#8211;(Marketwired &#8211; Nov 12, 2014) \u2013\u2013<\/strong> Plunify\u00aePte.Ltd., provider of groundbreaking field programmable gate array (FPGA) software, today announced its InTime\u2122 design optimization software provides support for Altera\u2019s FPGAs and systems on chip (SoCs).<\/p>\n<p>Plunify\u2019s InTime software harnesses computing resources and machine learning to rapidly generate optimized strategies for solving design problems.<\/p>\n<p>&#8220;We are pleased to have Plunify join our partner network,\u201d says Alex Grbic, director of software and IP marketing at Altera. \u201cWorking with companies like Plunify enables us to offer our customers a variety of complementary solutions.&#8221;<\/p>\n<p>Plunify\u2019s InTime software can provide Altera users a faster path to production. The InTime design optimization software evokes Altera\u2019s Quartus\u00ae II software to analyze designs and determine the best synthesis and place-and-route strategies. InTime has built-in intelligence to examine an FPGA design, derive correlations between the design, the FPGA device and the tool parameters, and subsequently provide users optimized strategies for synthesis and place-and-route. In one example, Huawei successfully deployed InTime in its production flow to close timing on multiple designs.<\/p>\n<p>Introduced in June, InTime uses statistical modeling and machine learning to draw insights from the data to improve quality of results. Furthermore, InTime has the ability to accumulate knowledge that can be applied to subsequent designs, or re-applied to the same design after it has been modified.<\/p>\n<p>\u201cWe are pleased to be part of the Altera ecosystem,\u201d remarks Harnhua Ng, Plunify\u2019s chief executive officer. \u201cThe evaluations we did with mutual customers and the benchmarking results show that InTime can be a valuable solution to analyze and manage multiple FPGA design compiles. Users appreciate InTime\u2019s machine learning feature because the engine gets better each time they run it.\u201d<\/p>\n<p><strong>About Plunify<\/strong><\/p>\n<p>Solutions from <a href=\"http:\/\/www.plunify.com\/\">Plunify\u00ae Pte. Ltd.<\/a> enable semiconductor chip designers to shorten product time to market and reduce development costs with no disruption to existing workflows. Its EDAxtend\u2122 cloud platform and InTime\u2122 timing closure tool help electronics companies meet FPGA design performance targets and significantly reduce their products\u2019 time to market. For more on Plunify\u2019s products, visit <a href=\"http:\/\/www.plunify.com\/\">www.plunify.com<\/a>.<\/p>\n<p><em>Plunify is a registered trademark of Plunify Pte. Ltd. EDAxtend is a trademark of Plunify. Plunify acknowledges trademarks or registered trademarks of other organizations for their respective products and services.<\/em><\/p>\n<p><strong>Media Contact:<\/strong><\/p>\n<p>Nanette Collins<br \/>\nPublic Relations for Plunify<br \/>\n(617) 437-1822[\/vc_column_text][\/vc_column][\/vc_row]<\/p>\n","protected":false},"excerpt":{"rendered":"<p>[vc_row row_type=&#8221;row&#8221; stretch_row_type=&#8221;no&#8221; css=&#8221;.vc_custom_1484623020079{margin-top: 20px !important;}&#8221;][vc_column][vc_column_text css=&#8221;.vc_custom_1486602199294{padding-top: 50px !important;}&#8221;] Press Releases [\/vc_column_text][\/vc_column][\/vc_row][vc_row row_type=&#8221;row&#8221; stretch_row_type=&#8221;no&#8221;][vc_column][vc_column_text] Plunify\u2019s InTime Design Optimization Software Supports Altera FPGAs and SoCs &nbsp; InTime Software Uses Advanced Computing Techniques to Accelerate Time to Production LOS ALTOS, CA&#8211;(Marketwired &#8211; Nov 12, 2014) \u2013\u2013 Plunify\u00aePte.Ltd., provider of groundbreaking field programmable gate array (FPGA) software, today [&hellip;]<\/p>\n","protected":false},"author":6,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"template-page-full-width-vc.php","meta":{"_links_to":"","_links_to_target":""},"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v17.0 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Press Releases, 12 Nov 2014 - Plunify \u6d66\u5229\u4e30<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.plunify.com\/cn\/pr20141112\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Press Releases, 12 Nov 2014 - Plunify \u6d66\u5229\u4e30\" \/>\n<meta property=\"og:description\" content=\"[vc_row row_type=&#8221;row&#8221; stretch_row_type=&#8221;no&#8221; css=&#8221;.vc_custom_1484623020079{margin-top: 20px !important;}&#8221;][vc_column][vc_column_text css=&#8221;.vc_custom_1486602199294{padding-top: 50px !important;}&#8221;] Press Releases [\/vc_column_text][\/vc_column][\/vc_row][vc_row row_type=&#8221;row&#8221; stretch_row_type=&#8221;no&#8221;][vc_column][vc_column_text] Plunify\u2019s InTime Design Optimization Software Supports Altera FPGAs and SoCs &nbsp; InTime Software Uses Advanced Computing Techniques to Accelerate Time to Production LOS ALTOS, CA&#8211;(Marketwired &#8211; Nov 12, 2014) \u2013\u2013 Plunify\u00aePte.Ltd., provider of groundbreaking field programmable gate array (FPGA) software, today [&hellip;]\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.plunify.com\/cn\/pr20141112\/\" \/>\n<meta property=\"og:site_name\" content=\"Plunify \u6d66\u5229\u4e30\" \/>\n<meta property=\"article:publisher\" content=\"https:\/\/www.facebook.com\/Plunify\" \/>\n<meta property=\"article:modified_time\" content=\"2017-02-09T01:03:16+00:00\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:site\" content=\"@plunify\" \/>\n<meta name=\"twitter:label1\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data1\" content=\"2 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"Organization\",\"@id\":\"https:\/\/www.plunify.com\/cn\/#organization\",\"name\":\"Plunify\",\"url\":\"https:\/\/www.plunify.com\/cn\/\",\"sameAs\":[\"https:\/\/www.facebook.com\/Plunify\",\"https:\/\/www.linkedin.com\/company\/611504\/\",\"https:\/\/www.youtube.com\/user\/Plunify\/\",\"https:\/\/twitter.com\/plunify\"],\"logo\":{\"@type\":\"ImageObject\",\"@id\":\"https:\/\/www.plunify.com\/cn\/#logo\",\"inLanguage\":\"en-US\",\"url\":\"https:\/\/www.plunify.com\/cn\/wp-content\/uploads\/sites\/10\/2017\/04\/logo-blueback.png\",\"contentUrl\":\"https:\/\/www.plunify.com\/cn\/wp-content\/uploads\/sites\/10\/2017\/04\/logo-blueback.png\",\"width\":812,\"height\":346,\"caption\":\"Plunify\"},\"image\":{\"@id\":\"https:\/\/www.plunify.com\/cn\/#logo\"}},{\"@type\":\"WebSite\",\"@id\":\"https:\/\/www.plunify.com\/cn\/#website\",\"url\":\"https:\/\/www.plunify.com\/cn\/\",\"name\":\"Plunify \\u6d66\\u5229\\u4e30\",\"description\":\"\\u4f18\\u5316\\u60a8\\u7684 FPGA \\u8bbe\\u8ba1\",\"publisher\":{\"@id\":\"https:\/\/www.plunify.com\/cn\/#organization\"},\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\/\/www.plunify.com\/cn\/?s={search_term_string}\"},\"query-input\":\"required name=search_term_string\"}],\"inLanguage\":\"en-US\"},{\"@type\":\"WebPage\",\"@id\":\"https:\/\/www.plunify.com\/cn\/pr20141112\/#webpage\",\"url\":\"https:\/\/www.plunify.com\/cn\/pr20141112\/\",\"name\":\"Press Releases, 12 Nov 2014 - Plunify \\u6d66\\u5229\\u4e30\",\"isPartOf\":{\"@id\":\"https:\/\/www.plunify.com\/cn\/#website\"},\"datePublished\":\"2017-02-07T06:01:38+00:00\",\"dateModified\":\"2017-02-09T01:03:16+00:00\",\"breadcrumb\":{\"@id\":\"https:\/\/www.plunify.com\/cn\/pr20141112\/#breadcrumb\"},\"inLanguage\":\"en-US\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\/\/www.plunify.com\/cn\/pr20141112\/\"]}]},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\/\/www.plunify.com\/cn\/pr20141112\/#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"Home\",\"item\":\"https:\/\/www.plunify.com\/cn\/\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"Press Releases, 12 Nov 2014\"}]}]}<\/script>\n<!-- \/ Yoast SEO plugin. -->","yoast_head_json":{"title":"Press Releases, 12 Nov 2014 - Plunify \u6d66\u5229\u4e30","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/www.plunify.com\/cn\/pr20141112\/","og_locale":"en_US","og_type":"article","og_title":"Press Releases, 12 Nov 2014 - Plunify \u6d66\u5229\u4e30","og_description":"[vc_row row_type=&#8221;row&#8221; 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