{"id":1405,"date":"2017-01-25T11:01:55","date_gmt":"2017-01-25T11:01:55","guid":{"rendered":"http:\/\/www.plunify.com\/cn\/?page_id=1405"},"modified":"2019-01-03T15:03:56","modified_gmt":"2019-01-03T07:03:56","slug":"news","status":"publish","type":"page","link":"https:\/\/www.plunify.com\/cn\/news\/","title":{"rendered":"\u5a92\u4f53\u62a5\u9053"},"content":{"rendered":"

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\u5a92\u4f53\u62a5\u9053<\/h2>\n

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\"EET\u82f1\u98de\u51cc\u5f00\u542f\u65b0\u52a0\u5761\u521b\u65b0\u4e2d\u5fc3
\n<\/a>EET Asia, 2018\u5e7410\u670828\u65e5<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"Semiconductor_engineering\"\u4e91\u8ba1\u7b97\u7684\u90a3\u4e9b\u201c\u5751\u201d
\n<\/a>Semiconductor Engineering, 2018\u5e7410\u670825\u65e5<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"logo-ECD\"\u519b\u4e8b\u4e0e\u822a\u7a7a\u8bbe\u8ba1\u7684\u65f6\u5e8f\u6536\u655b
\n<\/a>Embedded System Engineering, 2018\u5e7410\u670819\u65e5<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"EEweb\"\u57fa\u4e8e\u4e91\u8ba1\u7b97\u7684 FPGA \u8bbe\u8ba1\u5de5\u5177\u73b0\u5728\u6309\u9700\u4f9b\u5e94
\n<\/a>EEWeb, 2018\u5e7410\u670810\u65e5<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"Semiconductor_engineering\"\u4e91\u8ba1\u7b97\u9002\u5408\u82af\u7247\u8bbe\u8ba1\u5417\uff1f
\n<\/a>Semiconductor Engineering, 2018\u5e749\u670827\u65e5<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"EEjournalPlunify Cloud\u52a9\u529b\u8d5b\u7075\u601d\uff0c\u6309\u9700\u4f9b\u5e94\u7684\u8bbe\u8ba1\u5de5\u5177\u8ba9\u60a8\u9a6c\u5230\u6210\u529f<\/a>
\nEEJournal,\u00a02018\u5e749\u670818\u65e5<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"TechDesignForum\"EDA\u7231\u4e0a\u4eba\u5de5\u667a\u80fd
\n<\/a>Tech Design Forum, 2018\u5e746\u670826\u65e5<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"Semiconductor_engineering\"EDA \u5728\u4e91\u7aef2
\n<\/a>Semiconductor Engineering, 2018\u5e745\u67082\u65e5<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"Semiconductor_engineering\"EDA \u5728\u4e91\u7aef
\n<\/a>Semiconductor Engineering, 2018\u5e744\u670826\u65e5<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"Semiconductor_engineering\"\u672c\u5468\u8bbe\u8ba1\u603b\u7ed3
\n<\/a>Semiconductor Engineering, 2018\u5e746\u670822\u65e5<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"newelectronics\"\u89e3\u51b3\u53ef\u7f16\u7a0b\u5668\u4ef6\u7684\u62e5\u585e\u95ee\u9898<\/a>
\nNew Electronics, 2018\u5e744\u670811\u65e5<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"EEjournalPlunify\u643a\u624b\u817e\u8baf\u4e91\u5728\u4e91\u7aef\u4e3aFPGA\u5de5\u4f5c\u6d41\u7a0b\u52a0\u901f
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[\/vc_column_text][vc_column_text]<\/p>\n

\"EEjournalPlunify \u2013 FPGA\u5927\u6740\u5668<\/a>
\nEEJournal,\u00a02018\u5e742\u670813\u65e5<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"Semiconductor_engineering\"\u8fbe\u5230\u6027\u80fd\u7684\u6781\u9650
\n<\/a>Semiconductor Engineering, 2018\u5e742\u67088\u65e5<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"EEjournalPlunify \u53d1\u5e03 InTime \u4f18\u5316\u670d\u52a1\uff0c\u4e00\u5929\u4e4b\u5185\u5b9e\u73b0 FPGA \u8bbe\u8ba1\u7ed3\u679c<\/a>
\nEEJournal,\u00a02018\u5e742\u67087\u65e5<\/div>\n

[\/vc_column_text][\/vc_tta_section][vc_tta_section title=”2017\u5e74” tab_id=”1518142229723-84198eb1-f3b6″][vc_empty_space][vc_column_text]<\/p>\n

\"EEPW&Elecfans\u6d66\u5229\u4e30\u53d1\u5e03FPGA\u4e91\u5e73\u53f0\uff0c\u4e3a\u82af\u7247\u8bbe\u8ba1\u63d0\u4f9b\u4e91\u7aef\u4f18\u5316
\n\u7535\u5b50\u4ea7\u54c1\u4e16\u754c\u62a5\u9053<\/a>, \u7535\u5b50\u53d1\u70e7\u53cb\u62a5\u9053<\/a>, \u4e2d\u56fd\u7535\u5b50\u7f51\u62a5\u9053,<\/a>\u00a0\u5de5\u63a7\u7f51\u62a5\u9053<\/a>\uff0c2017\u5e7412\u67081\u65e5
\n<\/a><\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\u673a\u5668\u5b66\u4e60\u4f18\u5316FPGA\u65f6\u5e8f<\/a>
\n<\/a>SemiWiki.com, 2017\u5e748\u67084\u65e5
\n<\/a><\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"Semiconductor_engineering\"\u5f53\u673a\u5668\u5b66\u4e60\u4e0e IC \u8bbe\u8ba1\u76f8\u9047<\/a>
\n<\/a>Semiconductor Engineering, 2017\u5e746\u670829\u65e5
\n<\/a><\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"TDF\"2017\u5e74\u8bbe\u8ba1\u81ea\u52a8\u5316\u5927\u4f1a\u9884\u89c8 – Plunify
\n<\/a>Tech Design Forum, 2017\u5e746\u670816\u65e5
\n<\/a><\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"logo-ECD\"FPGA \u8bbe\u8ba1\u5e08\u8f6c\u5411\u4e91\u7aef\u7684\u673a\u5668\u5b66\u4e60<\/a>
\n<\/a>Embedded Computing Design, 2017\u5e746\u67089\u65e5
\n<\/a><\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"Analytics_India\"
\nPlunify\u6210\u4e3a\u65b0\u52a0\u5761\u5341\u4f73\u6570\u636e\u5206\u6790\u4f9b\u5e94\u5546\u4e4b\u4e00<\/a>
\nAnalytics India\uff0c2017\u5e745\u670815\u65e5<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"Eefocus&ElecfansPlunify\u5c06\u51fa\u5e2d5\u6708\u5728\u6210\u90fd\u548c\u957f\u6c99\u76842017 Xilinx All Programmable\u6280\u672f\u7814\u8ba8\u4f1a
\n\u4e0e\u975e\u7f51\u62a5\u9053<\/a>, \u7535\u5b50\u53d1\u70e7\u53cb\u62a5\u9053<\/a>\uff0c2017\u5e744\u670825\u65e5<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"Eefocus&ElecfansPlunify\u56de\u5f52\u81f3Amazon\u4e9a\u9a6c\u900aAWS\u7f51\u7edc\u670d\u52a1\u4e0a
\n\u4e0e\u975e\u7f51\u62a5\u9053<\/a>, \u7535\u5b50\u53d1\u70e7\u53cb\u62a5\u9053<\/a>\uff0c2017\u5e744\u670825\u65e5<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"Eefocus&ElecfansPlunify\u6210\u4e3aAmazon\u00a0EC2 F1 Instance Partner\u7684\u5408\u4f5c\u5382\u5bb6
\n\u4e0e\u975e\u7f51\u62a5\u9053<\/a>, \u7535\u5b50\u53d1\u70e7\u53cb\u62a5\u9053<\/a>\uff0c2017\u5e744\u670825\u65e5<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

Plunify \u6210\u4e3a\u65b0\u52a0\u5761\u5341\u5927\u98a0\u8986\u6027\u516c\u53f8\u4e4b\u4e00<\/a>
\nDisruptor Daily, 2017\u5e743\u670824\u65e5<\/div>\n

[\/vc_column_text][\/vc_tta_section][vc_tta_section title=”2016\u5e74” tab_id=”1493347539829-06806360-e956″][vc_empty_space][vc_column_text]\"logo_st\"Business possibilities in both Chengdu, Chongqing<\/a>
\nwww.straitstimes.com,\u00a02016\u5e748\u670830\u65e5[\/vc_column_text][vc_column_text]<\/p>\n

\"logo_ie\"
\nSingapore companies in education, technology and healthcare gain traction in Sichuan<\/a>
\nIE Singapore, 2016\u5e748\u670829\u65e5<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"logo_eefocus\"Plunify\u5c06\u4e0e\u6210\u90fd\u53cc\u6d41\u653f\u5e9c\u7b7e\u7f72MOU\u6295\u8d44\u5907\u5fd8\u5f55<\/a>
\n\u4e0e\u975e\u7f51, 2016\u5e748\u670826\u65e5<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"logo_eefocus\"Plunify\u5c06\u53c2\u52a0\u82f1\u7279\u5c14FPGA\u6280\u672f\u5927\u4f1a(IFTD) 2016<\/a>
\n\u4e0e\u975e\u7f51, 2016\u5e748\u670823\u65e5<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"logo_eefocus\"Plunify\u5c06\u51fa\u5e2d\u6df1\u5733\u7b2c\u4e5d\u5c4aAPEC SMETC2016<\/a>
\n\u4e0e\u975e\u7f51, 2016\u5e747\u67087\u65e5<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"elecfans\"Plunify\u5c06\u51fa\u5e2d\u6df1\u5733\u7b2c\u4e5d\u5c4a APEC SMETC2016<\/a>
\n\u7535\u5b50\u53d1\u70e7\u53cb, 2016\u5e747\u67087\u65e5<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"elecfans\"Plunify\u5728Altera\u5168\u7403\u5408\u4f5c\u4f19\u4f34\u4e2d\u626e\u6f14\u7684\u89d2\u8272\u548c\u5730\u4f4d<\/a>
\n\u7535\u5b50\u53d1\u70e7\u53cb, 2016\u5e747\u67086\u65e5<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"elecfans\"Mythbuster\u6d41\u8a00\u7ec8\u7ed3\u8005\uff1aInTime\u4e0eVivado 2016.1\u7684\u7248\u672c\u6bd4\u4ee5\u524d\u66f4\u597d\uff1f<\/a>
\n\u7535\u5b50\u53d1\u70e7\u53cb, 2016\u5e747\u67086\u65e5<\/div>\n

[\/vc_column_text][\/vc_tta_section][vc_tta_section title=”2015\u5e74” tab_id=”1485233966254-21735e06-a581″][vc_empty_space][vc_column_text]\"logo_fpgadesign\"\u4f7f\u7528Intime\u8f6f\u4ef6\u4f18\u5316FPGA\u65f6\u5e8f<\/a>
\nwww.fpgadesign.cn, October 11, 2015[\/vc_column_text][vc_column_text]\"logo_eejournal\"Plunify\u2019s FPGA Proof Point<\/a>
\nElectronic Engineering Journal,\u00a0March 03, 2015[\/vc_column_text][vc_column_text]\"logo_semiwiki\"Got FPGA Timing Closure Problems?<\/a>
\nSemiWiki.com, February 26, 2015[\/vc_column_text][vc_column_text]<\/p>\n

\"logo_mw\"
\nPlunify Launches “Results-Based” Pricing Model for FPGA Design Optimization Services<\/a>
\nMarket Wired, February 19, 2015<\/div>\n

[\/vc_column_text][vc_column_text]\"se\"With Responsibility Comes Power<\/a>
\nsemiengineering.com, February 12, 2015[\/vc_column_text][vc_column_text]\"se\"Plunify: FPGA Design Closure<\/a>
\nsemiengineering.com, February 09, 2015[\/vc_column_text][vc_column_text]\"chipdes\"The Coming Year in EDA: What Will Shape 2015<\/a>
\nChip Design, February 04, 2015[\/vc_column_text][vc_column_text]\"yf\"Plunify Appoints Altima Distributor in Japan<\/a>
\nYahoo! Finance, January 28, 2015[\/vc_column_text][vc_column_text]\"elecfans\"\u4e3aFPGA\u5de5\u7a0b\u5e08\u8282\u7701\u5341\u500d\u5f00\u53d1\u65f6\u95f4<\/a>
\nwww.elecfans.com, January 04, 2015[\/vc_column_text][\/vc_tta_section][vc_tta_section title=”2014\u5e74” tab_id=”1485344663814-e8fe786c-f395″][vc_empty_space][vc_column_text]\"finsmes\"Plunify completes funding<\/a>
\nFinSMEs, November 21, 2014[\/vc_column_text][vc_column_text]\"edacafe\"Plunify Closes Round of Funding With Investment From Lanza techVentures<\/a>
\nEDACafe, November 19, 2014[\/vc_column_text][vc_column_text]<\/p>\n

\"pehub\"
\nLanza techVentures backs Plunify<\/a>
\nPE HUB, November 19, 2014<\/div>\n

[\/vc_column_text][vc_column_text]\"yf\"Plunify Closes Round of Funding With Investment From Lanza techVentures<\/a>
\nYahoo Finance, November 19, 2014[\/vc_column_text][vc_column_text]<\/p>\n

\"eetimes_media\"Plunify’s InTime Now Supports Altera FPGAs & SoCs<\/a>
\nEETimes, November 13, 2014<\/div>\n

[\/vc_column_text][vc_column_text]\"embeddedcd\"Plunify’s InTime Design Optimization Software Supports Altera FPGAs and SoCs<\/a>
\nEmbedded Computing Design, November 12, 2014[\/vc_column_text][vc_column_text]\"yf\"Plunify’s InTime Design Optimization Software Supports Altera FPGAs and SoCs<\/a>
\nYahoo Finance, November 12, 2014[\/vc_column_text][vc_column_text]\"logo_chipdesign\"DAC Meanderings, 51st DAC 06_03<\/a>
\nChip Design Magazine, June 03, 2014[\/vc_column_text][vc_column_text]<\/p>\n

\"logo_eetasia\"SCI collaborates with Plunify, Optic2Connect for IC design<\/a>
\nEET Asia, June 03, 2014<\/div>\n

[\/vc_column_text][vc_column_text]\"logo_pradeeppoint\"Plunify\u2019s InTime helps FPGA design engineers meet timing and area goals!<\/a>
\nPradeep’s Point!, June 03, 2014[\/vc_column_text][vc_column_text]\"yf\"New Software From Plunify Solves FPGA Timing, Optimization Issues<\/a>
\nYahoo Finance, June 02, 2014[\/vc_column_text][\/vc_tta_section][vc_tta_section title=”2010-2013\u5e74” tab_id=”1485233983654-c3499a83-b1f7″][vc_empty_space][vc_text_separator title=”2013″ style=”shadow” el_width=”80″][vc_column_text]<\/p>\n

\"logo_ew\"
\nBig FPGA design moves to the cloud<\/a>
\nElectronicsWeekly.com, June 11, 2013<\/div>\n

[\/vc_column_text][vc_column_text]\"logo_newelectronics\"Plunify teams with Altera for fpga design in the cloud<\/a>
\nnewelectronics, June 5, 2013[\/vc_column_text][vc_column_text]Does Altera Have \u201cBig Data\u201d Communications on the Brain?<\/a>
\neecatalog.com\/caciufo, June 5, 2013[\/vc_column_text][vc_column_text]\"logo_wsj\"FPGA Design in the Cloud — Try It, You’ll Like It, Says Plunify<\/a>
\nThe Wall Street Journal, June 4 , 2013[\/vc_column_text][vc_column_text]\"logo_soccentral\"Plunify Cloud Platform Accelerates Chip Design Workflow, Now Offers Altera’s Quartus II<\/a>
\nSOCcentral, June 4 , 2013<\/span>[\/vc_column_text][vc_column_text]<\/p>\n

\"logo_cnw\"\u5316\u4e91\u4e3a\u96e8 \u4e91\u8ba1\u7b97\u52a9\u529bIC\u8bbe\u8ba1<\/a>
\nChina Network World, March 28, 2013<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"logo_ed\"
\nCheck Out Chip Designs On The Cloud<\/a>
\nElectronic Design, March 26, 2013<\/div>\n

[\/vc_column_text][vc_column_text]\"logo_eepw\"\u4e91\u65f6\u4ee3\u624d\u521a\u521a\u5f00\u59cb – Plunify\uff1a\u628a\u8bbe\u8ba1\u653e\u5728\u4e91\u7aef<\/a>
\nEEPW, March 18, 2013[\/vc_column_text][vc_column_text]<\/p>\n

\"logo_controlengineering\"Plunify\u4e91\u670d\u52a1\u6216\u5927\u5e45\u63d0\u5347\u56fd\u5185\u4e2d\u5c0f\u4f01\u4e1aFPGA\u521b\u65b0\u80fd\u529b<\/a>
\nControl Engineering China, March 15, 2013<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"logo_cnw\"Plunify\u4e91\u5e73\u53f0\u53d1\u6325\u5e73\u53f0\u6574\u5408\u4f18\u52bf \u964d\u4f4eIC\u8bbe\u8ba1\u6210\u672c<\/a>
\nChina Network World, March 12, 2013<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"logo_cnw\"Plunify\u9ec4\u701a\u534e\uff1a\u5de5\u7a0b\u4e91\u5e73\u53f0\u5f15\u9886\u5de5\u7a0b\u8bbe\u8ba1\u65b0\u8d8b\u52bf<\/a>
\nChina Network World, March 12, 2013<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"logo_zdnetcn\"Plunify\u505a\u5356\u6c34\u4eba \u4e3a\u82af\u7247\u8bbe\u8ba1\u63d0\u4f9b\u4e91\u7aef\u670d\u52a1<\/a>
\nZDNET, March 11, 2013<\/div>\n

[\/vc_column_text][vc_column_text]\"logo_chinacloud\"Plunify\u505a\u5356\u6c34\u4eba \u4e3a\u82af\u7247\u8bbe\u8ba1\u63d0\u4f9b\u4e91\u7aef\u670d\u52a1<\/a>
\n\u4e2d\u4e91, March 11, 2013[\/vc_column_text][vc_column_text]\"logo_d1net\"Plunify\u8fdb\u519b\u5927\u9646 \u5411\u4e91\u670d\u52a1\u63d0\u4f9b\u5546\u629b\u51fa\u6a44\u6984\u679d<\/a>
\n\u4f01\u4e1a\u7f51, March 11, 2013[\/vc_column_text][vc_column_text]<\/p>\n

\"logo_cctime\"Plunify\u8fdb\u519b\u5927\u9646 \u5411\u4e91\u670d\u52a1\u63d0\u4f9b\u5546\u629b\u51fa\u6a44\u6984\u679d<\/a>
\nCCTiME \u98de\u8c61\u7f51, March 11, 2013<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"logo_sohu\"Plunify\u8fdb\u519b\u5927\u9646 \u5411\u4e91\u670d\u52a1\u63d0\u4f9b\u5546\u629b\u51fa\u6a44\u6984\u679d<\/a>
\n\u641c\u72d0, March 11, 2013<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"logo_eefocus\"\u5728\u7ebf\u7535\u8def\u8bbe\u8ba1\u79bb\u6211\u4eec\u8fd8\u6709\u591a\u8fdc<\/a>
\nEEFOCUS \u4e0e\u975e\u7f51, March 11, 2013<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"elecfans\"Plunify\uff1a\u4e91\u5e73\u53f0\u53d1\u6325\u6574\u5408\u4f18\u52bf \u964d\u4f4eIC\u8bbe\u8ba1\u6210\u672c<\/a>
\n\u7535\u5b50\u53d1\u70e7\u53cb, March 8, 2013<\/div>\n

[\/vc_column_text][vc_column_text]\"logo_doitcloud\"Plunify\u9ec4\u701a\u534e\uff1a\u5de5\u7a0b\u4e91\u5e73\u53f0\u5f15\u9886\u5de5\u7a0b\u8bbe\u8ba1\u65b0\u8d8b\u52bf<\/a>
\nDOiT, March 8, 2013[\/vc_column_text][vc_column_text]<\/p>\n

\"logo_ickey\"Plunify\uff1a\u4e91\u5e73\u53f0\u6574\u5408EDA\u5de5\u5177\uff0c\u8ba9\u8bbe\u8ba1\u5728\u4e91\u7aef\u5b8c\u6210<\/a>
\nICKEY, March 8, 2013<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"logo_eeworld\"Plunify\uff1a\u4e91\u5e73\u53f0\u6574\u5408EDA\u5de5\u5177\uff0c\u8ba9\u8bbe\u8ba1\u5728\u4e91\u7aef\u5b8c\u6210<\/a>
\neeworld, March 7, 2013<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"logo_ctocio\"
\nPlunify\u9ec4\u701a\u534e\uff1a\u5de5\u7a0b\u4e91\u5e73\u53f0\u5f15\u9886\u5de5\u7a0b\u8bbe\u8ba1\u65b0\u8d8b\u52bf<\/a>
\nIT\u4e13\u5bb6\u7f51, March 7, 2013<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"logo_doit\"Plunify\u4e3a\u82af\u7247\u8bbe\u8ba1\u63d0\u4f9b\u6700\u4f73\u4e91\u670d\u52a1<\/a>
\nDOiT, March 7, 2013<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"logo_chinaaet\"Plunify\u4e91\u7aef\u6280\u672f\u52a0\u901f\u4f18\u5316\u82af\u7247\u8bbe\u8ba1<\/a>
\n\u7535\u5b50\u6280\u672f\u5e94\u7528, March 7, 2013<\/div>\n

[\/vc_column_text][vc_column_text]\"logo_hexun\"\u6210\u672c\u4e0d\u803d\u8bef\u6548\u7387\uff1a\u82af\u7247\u8bbe\u8ba1\u4e5f\u53ef\u6c72\u53d6\u516c\u6709\u4e91\u7684\u529b\u91cf<\/a>
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\nZDNET, March 7, 2013<\/div>\n

[\/vc_column_text][vc_column_text]\"logo_caigou\"Plunify\uff1a\u4e91\u5e73\u53f0\u53d1\u6325\u6574\u5408\u4f18\u52bf \u964d\u4f4eIC\u8bbe\u8ba1\u6210\u672c<\/a>
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\nIT\u4e13\u5bb6\u7f51, March 6, 2013<\/div>\n

[\/vc_column_text][vc_column_text]\"logo_semiconductortimes\"Startup Profiles \u2013 Plunify<\/a>
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\nDSP-FPGA.com, February 13, 2013[\/vc_column_text][vc_column_text]\"logo_eejournal\"The Elephant in the Cloud<\/a>
\nElectronic Engineering Journal, February 12, 2013[\/vc_column_text][vc_column_text]\"logo_eecatalog\"Practical applications of cloud computing in semiconductor chip design<\/a>
\nEECatalog, February 6, 2013[\/vc_column_text][vc_column_text]\"logo_chipdesign\"Practical applications of cloud computing in semiconductor chip design<\/a>
\nChip Design Magazine, February, 2013[\/vc_column_text][vc_column_text]<\/p>\n

\"logo_inc\"Spotted at CES: Singapore Start-ups<\/a>
\nINC., January 11, 2013<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"logo_ept\"
\nFPGA design heads to the Cloud<\/a>
\nEP&T, January 8, 2013<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"logo_eetasia\"Start-up takes FPGA design to the cloud<\/a>
\nEET Asia, January 8, 2013<\/div>\n

[\/vc_column_text][vc_column_text]<\/p>\n

\"logo_zdnet\"
\nPartnerships, exposure top S’pore firms’ CES wishlists<\/a>
\nZDNet, January 2, 2013<\/div>\n

[\/vc_column_text][vc_column_text]\"eetimes_media\"Plunify, net-based FPGA design startup, gains funds<\/a>
\nEETimes, January 4, 2013[\/vc_column_text][vc_text_separator title=”2012″ style=”shadow” el_width=”80″][vc_column_text]<\/p>\n

\"logo_mem\"
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\n\u65b0\u96fb\u5b50\u79d1\u6280\u96dc\u8a8c Micro-Electronics Magazine, December 19, 2012<\/div>\n

[\/vc_column_text][vc_column_text]\"logo_pradeeppoint\"FPGA design heads to the cloud!<\/a>
\nPradeep’s Point!, December 6, 2012[\/vc_column_text][vc_column_text]<\/p>\n

\"logo_e27\"(Valleys of the East \u2013 Innovative startups in Asia) Plunify recognized this problem and built a smart platform for ‘Cloud-accelerated Chip Design’. On top of Amazon Web Services’ cloud infrastructure …<\/a>
\nE27, May 18, 2012<\/div>\n

[\/vc_column_text][vc_column_text]\"canadianelectronics\"The Cloud brings FPGAs and EDA down to earth<\/a>
\nCanadian Electronics, May 4, 2012[\/vc_column_text][vc_text_separator title=”2011″ style=”shadow” el_width=”80″][vc_column_text]<\/p>\n

\"PBAWS_LOGO_127px\"Plunify is now part of Amazon Web Services Solution Providers Program<\/a>
\nAmazon Web Services, October 24, 2011<\/div>\n

[\/vc_column_text][vc_column_text]\"olivier_media\"Why EDA in the cloud will come from startups<\/a>
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\nDangerous Prototypes, July 7, 2011[\/vc_column_text][vc_column_text]\"dangporoto\"Plunify Interview Questions<\/a>\u00a0and forum<\/a>
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\"eetimes_media\"
\nPlunify launches SaaS platform that integrates FPGA design tools<\/a>
\nEETimes, December 8, 2010<\/div>\n

[\/vc_column_text][vc_column_text]\"olivier_media\"Plunify, A Glimpse At EDA In The Cloud<\/a>
\nOlivier Coudert, September 7, 2010[\/vc_column_text][vc_column_text]\"sigasi_media\"A New EDA 2.0 Company: Plunify<\/a>
\nSigasi, August 24, 2010[\/vc_column_text][\/vc_tta_section][\/vc_tta_tabs][\/vc_column][vc_column width=”1\/4″][vc_message]<\/p>\n

\u516c\u5173\u54a8\u8be2<\/h4>\n

\u9ec4\u701a\u534e\u5148\u751f
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