{"id":1372,"date":"2017-01-24T05:26:19","date_gmt":"2017-01-24T05:26:19","guid":{"rendered":"http:\/\/www.plunify.com\/cn\/?page_id=1372"},"modified":"2019-01-03T16:00:47","modified_gmt":"2019-01-03T08:00:47","slug":"events","status":"publish","type":"page","link":"https:\/\/www.plunify.com\/cn\/events\/","title":{"rendered":"\u6d3b\u52a8"},"content":{"rendered":"

[vc_row row_type=”row” stretch_row_type=”no” css=”.vc_custom_1484623020079{margin-top: 20px !important;}”][vc_column][vc_column_text css=”.vc_custom_1492745289479{padding-top: 50px !important;}”]<\/p>\n

\u6d3b\u52a8<\/h2>\n

[\/vc_column_text][\/vc_column][\/vc_row][vc_row row_type=”row” stretch_row_type=”no”][vc_column width=”3\/4″][vc_tta_tabs style=”modern” color=”sky” active_section=”1″][vc_tta_section title=”\u6700\u65b0” tab_id=”1485233924333-83b62f38-9739″][vc_empty_space][vc_column_text]\u6d3b\u52a8\uff1aPaltek \u4e3e\u529e\u7684\u673a\u5668\u5b66\u4e60\u4f18\u5316FPGA\u8bbe\u8ba1\u7814\u8ba8\u4f1a<\/a>\"Paltek\"<\/a><\/strong>
\nPaltek \u57282018\u5e7412\u670814\u65e5\u4e3e\u529e InTime \u548c\u673a\u5668\u5b66\u4e60\u7684\u6f14\u8bb2\u4f1a\uff08\u4ec5\u9650\u65e5\u8bed\uff09\u3002
\n\u65e5\u671f\uff1a2018\u5e7412\u670814\u65e5
\n\u5730\u70b9\uff1a\u65b0\u6a2a\u6ee8[\/vc_column_text][vc_column_text]\"XDF_2017\"\u6d3b\u52a8\uff1a2018\u5e74\u8d5b\u7075\u601d\u5f00\u53d1\u8005\u5927\u4f1a – \u6cd5\u5170\u514b\u798f<\/a><\/strong>
\nPlunify \u5c06\u57282018\u5e74\u8d5b\u7075\u601d\u5f00\u53d1\u8005\u5927\u4f1a\u4ecb\u7ecd\u5168\u65b0\u5347\u7ea7\u7684 Plunify Cloud \u4e91\u5e73\u53f0\uff0c\u4ee5\u53ca\u5e73\u53f0\u4e0a\u7684 FPGA Expansion Pack\uff0cAI Lab\uff0cInTime \u7b49\u5e94\u7528\u3002Plunify \u4f4d\u4e8e1\u53f7\u5c55\u53f0\u3002
\n\u65e5\u671f\uff1a2018\u5e7412\u670810\u65e5
\n\u5730\u70b9\uff1a\u5fb7\u56fd\u6cd5\u5170\u514b\u798f\uff0c\u4e07\u8c6a\u9152\u5e97[\/vc_column_text][vc_column_text]\"XDF_2017\"\u6d3b\u52a8\uff1a2018\u5e74\u8d5b\u7075\u601d\u5f00\u53d1\u8005\u5927\u4f1a – \u5317\u4eac<\/a><\/strong>
\nPlunify\u5c06\u57282018\u5e74\u8d5b\u7075\u601d\u5f00\u53d1\u8005\u5927\u4f1a\u4ecb\u7ecd\u5168\u65b0\u5347\u7ea7\u7684 Plunify Cloud \u4e91\u5e73\u53f0\uff0c\u4ee5\u53ca\u5e73\u53f0\u4e0a\u7684 FPGA Expansion Pack\uff0cAI Lab\uff0cInTime\u7b49\u5e94\u7528\u3002
\n\u65e5\u671f\uff1a 2018\u5e7410\u670816\u65e5
\n\u5730\u70b9\uff1a\u5317\u4eac\u56fd\u9645\u996d\u5e97[\/vc_column_text][vc_column_text]\"XDF_2017\"\u6d3b\u52a8\uff1a2018\u5e74\u8d5b\u7075\u601d\u5f00\u53d1\u8005\u5927\u4f1a – \u7845\u8c37<\/a><\/strong>
\nPlunify\u5c06\u57282018\u5e74\u8d5b\u7075\u601d\u5f00\u53d1\u8005\u5927\u4f1a\u4ecb\u7ecd\u5168\u65b0\u5347\u7ea7\u7684 Plunify Cloud \u4e91\u5e73\u53f0\uff0c\u4ee5\u53ca\u5e73\u53f0\u4e0a\u7684 FPGA Expansion Pack\uff0cAI Lab\uff0cInTime\u7b49\u5e94\u7528\u3002Plunify \u4f4d\u4e8e24\u53f7\u5c55\u53f0\u3002
\n\u65e5\u671f\uff1a 2018\u5e7410\u67081-2\u65e5
\n\u5730\u70b9\uff1a\u7f8e\u56fd\u5723\u4f55\u585e\uff0c\u8d39\u5c14\u8499\u9152\u5e97[\/vc_column_text][vc_column_text]\"IFTD2017\"\u6d3b\u52a8\uff1a2018\u5e74\u82f1\u7279\u5c14 FPGA \u6280\u672f\u5927\u4f1a<\/a><\/strong>
\nPlunify\u5c06\u57282018\u5e74\u82f1\u7279\u5c14FPGA\u6280\u672f\u5927\u4f1a\uff08IFTD 2018\uff09\u5c55\u793a\u6700\u65b0\u6b3e InTime\u3002
\n\u65e5\u671f\uff1a 2018\u5e749\u670821\u65e5
\n\u5730\u70b9\uff1a\u4e1c\u4eac\u96c5\u53d9\u56ed\u9152\u5e97<\/p>\n

[\/vc_column_text][vc_column_text]\"logo_dac55\"\u6d3b\u52a8: 2018\u8bbe\u8ba1\u81ea\u52a8\u5316\u5927\u4f1a \uff08Design Automation Conference 2018\uff09<\/a><\/strong>
\n\u73b0\u573a\u4f53\u9a8c\u6700\u65b0\u7248\u7684 InTime 2.6\u548c Plunify Cloud\uff01\u6211\u4eec\u57282124\u53f7\u5c55\u53f0\u3002
\n\u65e5\u671f\uff1a2018\u5e746\u670824-28\u65e5
\n\u5730\u70b9\uff1a\u7f8e\u56fd\u65e7\u91d1\u5c71 Moscone Center[\/vc_column_text][\/vc_tta_section][vc_tta_section title=”2017\u5e74” tab_id=”1537243351350-abb54b89-19fb”][vc_empty_space][vc_column_text]\"XDF_2017\"\u6d3b\u52a8\uff1a2017\u5e74\u8d5b\u7075\u601d\u5f00\u53d1\u8005\u5927\u4f1a<\/a><\/strong>
\nPlunify\u5c06\u57282017\u5e74\u8d5b\u7075\u601d\u5f00\u53d1\u8005\u5927\u4f1a\u53d1\u5e03\u5168\u65b0\u4e91\u5e73\u53f0 Plunify Cloud\u3002
\n\u65e5\u671f: 2017\u5e7410\u670819\u65e5\uff0c \u00a0\u5730\u70b9\uff1a\u5317\u4eac[\/vc_column_text][vc_column_text]\"IFTD2017\"\u6d3b\u52a8\uff1a2017\u5e74\u82f1\u7279\u5c14 FPGA \u6280\u672f\u5927\u4f1a<\/a><\/strong>
\nPlunify\u5c06\u57282017\u5e74\u82f1\u7279\u5c14FPGA\u6280\u672f\u5927\u4f1a\uff08IFTD 2017\uff09\u5c55\u793a InTime \u5728 Stratix 10 \u9879\u76ee\u4e0a\u7684\u4f18\u5316\u6027\u80fd\u3002
\n\u65e5\u671f: 2017\u5e749\u670814\u65e5\uff0c \u00a0\u5730\u70b9\uff1a\u6df1\u5733
\n\u65e5\u671f: 2017\u5e749\u670819\u65e5\uff0c \u00a0\u5730\u70b9\uff1a\u5317\u4eac
\n\u65e5\u671f: 2017\u5e749\u670826\u65e5\uff0c \u00a0\u5730\u70b9\uff1a\u6210\u90fd[\/vc_column_text][vc_column_text]\u6d3b\u52a8\uff1aPaltek \u4e3e\u529e\u7684 InTime \u7814\u8ba8\u4f1a<\/a>\"Paltek\"<\/a><\/strong>
\nPaltek \u57282017\u5e749\u67081\u65e5\u4e3e\u529e InTime \u548c\u673a\u5668\u5b66\u4e60\u7684\u6f14\u8bb2\u4f1a\uff08\u4ec5\u9650\u65e5\u8bed\uff09\u3002
\n\u65e5\u671f\uff1a2017\u5e749\u67081\u65e5
\n\u5730\u70b9\uff1a\u65b0\u6a2a\u6ee8[\/vc_column_text][vc_column_text]\"Moore\"\u6d3b\u52a8: \u57fa\u4e8e\u673a\u5668\u5b66\u4e60\u7684FPGA\u65f6\u5e8f\u4f18\u5316\u5927\u5e08\u5b9e\u4f8b\u6f14\u793a<\/a><\/strong>
\n\u672c\u671f\u4e3b\u8981\u4ecb\u7ecdFPGA\u4f18\u5316\u540e\u7aef\u65f6\u5e8f\u7684\u4e00\u4e9b\u5e38\u7528\u65b9\u6cd5\uff0c\u7740\u91cd\u4ecb\u7ecdPlunify\u516c\u53f8\u63a8\u51fa\u7684\u65f6\u5e8f\u4f18\u5316\u5927\u5e08—InTime\u8f6f\u4ef6\uff0c\u5e76\u8fdb\u884c\u4e86\u5b9e\u4f8b\u6f14\u793a\u3002
\n\u65e5\u671f\uff1a2017\u5e747\u670810\u65e5
\n\u5730\u70b9\uff1a\u6469\u5c14\u76f4\u64ad\u5b66\u4e60\u7fa4 (\u7ebf\u4e0a\uff09[\/vc_column_text][vc_column_text]\"logo_dac54\"\u6d3b\u52a8: 2017\u8bbe\u8ba1\u81ea\u52a8\u5316\u5927\u4f1a \uff08Design Automation Conference 2017\uff09<\/a><\/strong>
\n\u5e26\u4e0a\u4f60\u7684FPGA\u8bbe\u8ba1\uff0c\u770b\u770b\u6211\u4eec\u662f\u600e\u6837\u5728\u73b0\u573a\u4f18\u5316\u5b83\u7684\u6027\u80fd\u7684\uff01\u6211\u4eec\u57281631\u53f7\u5c55\u53f0\u3002
\n\u65e5\u671f\uff1a2017\u5e746\u670818-22\u65e5
\n\u5730\u70b9\uff1a\u7f8e\u56fd\u5fb7\u5dde\u5965\u65af\u4e01\u4f1a\u5c55\u4e2d\u5fc3 (Austin Convention Center, Texas)[\/vc_column_text][vc_column_text]\"Xilinx<\/p>\n

\u6d3b\u52a8\uff1aXilinx All Programmable \u6280\u672f\u7814\u8ba8\u4f1a<\/strong><\/a>
\n\u6b22\u8fce\u6765Xilinx All Programmable \u6280\u672f\u7814\u8ba8\u4f1a\uff0c\u4e86\u89e3\u66f4\u591a\u5173\u4e8eInTime\u7684\u4fe1\u606f\u5e76\u89c2\u770b\u5c55\u793a\u3002Plunify \u5c06\u5728\u79d1\u901a\u96c6\u56e2\u7684\u5c55\u53f0\u3002
\n\u65e5\u671f\uff1a2017\u5e745\u67083\u65e5\uff0c\u5730\u70b9\uff1a\u6210\u90fd\u4e3d\u90fd\u559c\u6765\u767b\u9152\u5e97
\n\u65e5\u671f\uff1a2017\u5e745\u67085\u65e5\uff0c\u5730\u70b9\uff1a\u957f\u6c99\u7687\u51a0\u5047\u65e5\u9152\u5e97[\/vc_column_text][\/vc_tta_section][vc_tta_section title=”2016\u5e74” tab_id=”1491883172381-6065419b-cce4″][vc_empty_space][vc_column_text]\"logo_iftd\"Event: IFTD16 (INTEL FPGA Technology Day)<\/strong><\/a>
\n25 August, 2016 – Singapore
\n8 September, 2016 – Hangzhou, China
\n13 September, 2016 – Chengdu, China[\/vc_column_text][vc_column_text]\"logo_smetc\"Event: APEC SMETC2016 (\u7b2c\u4e5d\u5c4aAPEC\u4e2d\u5c0f\u4f01\u4e1a\u6280\u672f\u4ea4\u6d41\u66a8\u5c55\u89c8\u4f1a)<\/strong><\/a>
\nSmall & Medium Enterprises Technology Conference and Fair
\n14 – 16 July, 2016
\nShenzhen Convention & Exhibition Center, China[\/vc_column_text][vc_column_text]\"innovfest\"Event: InnovFest unBound 2016<\/strong><\/a>
\nLargest innovation festival in South East Asia
\n17 – 18 May, 2016
\nLevel 5, Marina Bay Sands Convention Centre, 10 Bayfront Ave, Singapore[\/vc_column_text][vc_column_text]\"conf_icon\"Event: Optimizing Classification for Learning-Driven Timing Closure of FPGA Designs<\/strong><\/a>
\nInternational Symposium on Field-Programmable Custom Computing Machines
\nMay, 2016[\/vc_column_text][vc_column_text]\"conf_icon\"Event: Reliable Timing Closure for FPGA Designs through Machine Learning<\/strong><\/a>
\nInternational Symposium on Field-Programmable Gate Arrays
\nFebruary, 2016[\/vc_column_text][\/vc_tta_section][vc_tta_section title=”2015\u5e74” tab_id=”1485233966254-21735e06-a581″][vc_empty_space][vc_column_text]\"semisr_logo\"Event: SemIsrael Expo 2015<\/strong><\/a>
\n17 November 2015
\nAvenue Convention Center, Airport City, Israel[\/vc_column_text][vc_column_text]\"conf_icon\"Paper presentation – Driving Timing Convergence of FPGA Designs through Machine Learning and Cloud Computing The 23rd IEEE International Symposium on Field-Programmable Custom Computing Machines<\/strong><\/a>
\nMay 3-5, 2015
\nVancouver, British Columbia, Canada[\/vc_column_text][vc_column_text]\"conf_icon\"Paper presentation – InTime: A Machine Learning Approach for Efficient Selection of FPGA CAD Tool Parameters 23rd ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays<\/strong><\/a>
\nFebruary 22 – 24, 2015
\nMonterey Conference Center, Monterey, California[\/vc_column_text][vc_column_text]\"webinarimg\"Webinar – Got FPGA Timing Closure Problems?<\/strong><\/a>
\nWatch Plunify\u2019s webinar to learn how to solve your most difficult timing problems.
\nMarch 10, 2015[\/vc_column_text][\/vc_tta_section][vc_tta_section title=”2011-2014\u5e74” tab_id=”1485233983654-c3499a83-b1f7″][vc_empty_space][vc_text_separator title=”2014″ style=”shadow” el_width=”80″][vc_column_text]
\n\"logo_dac50\"Event: Design Automation Conference 2014 (San Francisco)<\/strong><\/a>
\nVisit us on June 1 – 5, 2014
\nMoscone Center[\/vc_column_text][vc_text_separator title=”2013″ style=”shadow” el_width=”80″][vc_column_text]\"logo_dac50\"<\/a>Event: Design Automation Conference 2013 (Austin)<\/a><\/strong>
\nVisit us on June 5, 2013
\nLocation: Austin, Texas[\/vc_column_text][vc_column_text]\"logo_ces\"Event: Suite Innovation, Consumer Electronics Show <\/strong><\/a>
\nVisit us on January 8-11, 2013
\nVenetian Palazzo Hospitality Suite, Venetian Tower, Las Vegas[\/vc_column_text][vc_text_separator title=”2012″ style=”shadow” el_width=”80″][vc_column_text]\"logo_dac50\"Event: Design Automation Conference 2012
\n(San Francisco)<\/strong><\/a>
\nVisit us on June 6, 2012
\nTime: 12:30 PM – 1:30 PM
\nLocation: Room 105 (Exhibit Floor)[\/vc_column_text][vc_column_text]
\n\"logo\"Event: SEMICON Singapore 2012<\/strong><\/a>
\nPlunify had the opportunity to showcase FPGAAccel and the capabilities of its cloud platform at this annual semiconductor industry event.
\nApril 24 – 26, 2012
\nMarina Bay Sands Expo & Convention Center[\/vc_column_text][vc_text_separator title=”2011″ style=”shadow” el_width=”80″][vc_column_text]\"event_01\"Event: Accelerate Time-To-Market Using Cloud Computing <\/strong><\/a>
\nOrganized by the Singapore Semiconductor Industry Association (SSIA), Plunify presents a case of “What can FPGA designers do with their own personal data centers”. (Slides<\/a>)
\nOctober 14, 2011[\/vc_column_text][vc_column_text]Adventures at DAC<\/a>\"logo_dac50\"<\/a><\/strong>
\nPlunify was at Design Automation Conference meeting up with tool and IP partners. The Design Automation Conference is the world’s leading technical conference and trade show on electronic design automation. For over 48 years, DAC remains the world\u2019s premier conference on Electronic Design Automation (EDA).
\nJun, 2011[\/vc_column_text][\/vc_tta_section][\/vc_tta_tabs][\/vc_column][vc_column width=”1\/4″][vc_message]<\/p>\n

\u516c\u5173\u54a8\u8be2<\/h4>\n

\u9ec4\u701a\u534e\u5148\u751f
\nmedia@plunify.com<\/a>[\/vc_message][\/vc_column][\/vc_row]<\/p>\n","protected":false},"excerpt":{"rendered":"

[vc_row row_type=”row” stretch_row_type=”no” css=”.vc_custom_1484623020079{margin-top: 20px !important;}”][vc_column][vc_column_text css=”.vc_custom_1492745289479{padding-top: 50px !important;}”] \u6d3b\u52a8 [\/vc_column_text][\/vc_column][\/vc_row][vc_row row_type=”row” stretch_row_type=”no”][vc_column width=”3\/4″][vc_tta_tabs style=”modern” color=”sky” active_section=”1″][vc_tta_section title=”\u6700\u65b0” tab_id=”1485233924333-83b62f38-9739″][vc_empty_space][vc_column_text]\u6d3b\u52a8\uff1aPaltek \u4e3e\u529e\u7684\u673a\u5668\u5b66\u4e60\u4f18\u5316FPGA\u8bbe\u8ba1\u7814\u8ba8\u4f1a Paltek \u57282018\u5e7412\u670814\u65e5\u4e3e\u529e InTime \u548c\u673a\u5668\u5b66\u4e60\u7684\u6f14\u8bb2\u4f1a\uff08\u4ec5\u9650\u65e5\u8bed\uff09\u3002 \u65e5\u671f\uff1a2018\u5e7412\u670814\u65e5 \u5730\u70b9\uff1a\u65b0\u6a2a\u6ee8[\/vc_column_text][vc_column_text]\u6d3b\u52a8\uff1a2018\u5e74\u8d5b\u7075\u601d\u5f00\u53d1\u8005\u5927\u4f1a – \u6cd5\u5170\u514b\u798f Plunify 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