The Vivado® Design Suite delivers a SoC-strength, IP-centric and system-centric, next generation development environment that has been built from the ground up to address the productivity bottlenecks in system-level integration and implementation. The Vivado Design suite is a Generation Ahead in overall productivity, ease-of-use, and system level integration capabilities.
Plunify is part of the Xilinx Alliance Program. Vivado supports the following device families: Ultrascale, Virtex-7, Kintex-7, Artix-7, and Zynq -7000
Onespin 360 DV-Inspect 360 DV-Inspect increases the productivity of existing design and verification flows by adding push-button formal analysis. This formal analysis can start once the design under test (DUT) can be compiled – independent of testbenches.
This way, critical bugs can be found much earlier with 360 DV-Inspect than with a purely simulation-based flow. In addition 360 DV’s formal technology allows to actually prove the absence of potential problems like synthesis-simulation mismatches, thus ensuring the absence of unpleasant surprises much later in the design flow.
The ISE Design Suite is a complete RTL to bit stream design flow that provides the fundamental tools, technologies and familiar design flow to achieve optimal design results. These include intelligent clock gating for dynamic power reduction, team design for multi-site design teams, design preservation for timing repeatability, and a partial reconfiguration option for greater system flexibility, size, power, and cost reduction.
Plunify is part of the Xilinx Alliance Program. ISE supports the following device families and their previous generations: Spartan-6, Virtex-6, and Coolrunner.