We have a free tier of basic services to get users up to speed quickly. Simulation, synthesis, place-and-route, customized benchmarking and verification services tailored to specific needs are available.
It depends on what stage of the process you are in.
If you have started coding, probably simulation is the logical next step. After that, compiling and verifying your design using the online tools complete the picture.
If you are conceptualizing, it should help to look for a similar reference design as a point of reference, or simply start prototyping.
Currently our platform supports Verilog and VHDL, the most common languages used for hardware design. If you would like to have more, give us a shout at
tellus@plunify.com!
Have a look at their respective websites:
Icarus Verilog and
GHDL.
Icarus Verilog
Your code is run through a two-part process.
A logfile is generated at each stage with information that might be useful for debugging.
1) Compilation to check syntax and derive a simulatable file -> iverilog.log
2) Run to execute the actual simulation -> vvp.log
GHDL
Your code is run through a three-part process.
A logfile is generated at each stage with information that might be useful for debugging.
1) Compilation or Analysis to check syntax and semantics -> analysis.log
2) Elaboration to flatten the design hierarchy, create ports and signals -> elaboration.log
3) Run to execute the actual simulation -> run.log
Certainly--we are working on making all the features of these great tools available to you.
We are staying out of that debate! Feel free to try both on our platform. For more "passionate" discourse on this, please google related topics ; )
Yes, in the Simulation Panel, simply select the appropriate vendor simulation libraries from the provided list.
Note: For GHDL, the analysis and elaboration options "--ieee=synopsys -fexplicit" will be used by default.
To ensure that your simulation will not run infinitely, by default we add a module called "plunifyendsim" which terminates a simulation after 100 million simulation cycles.
If desired, you can change the simulation duration and time unit by entering appropriate values in the Simulation Panel.
Either not all modules have the same timescale, or some modules are missing timescales. If you specify a simulation duration using the Simulation Panel, that timescale is automatically imposed on your simulation.
By default, Icarus Verilog will run for 100 million cycles, and GHDL for 1 millisecond.
There are several options to end a simulation:
- In your code, have statements like $finish or $stop in Verilog and "assert ..." in VHDL to ensure that the simulation does not run forever.
- In the Simulation Panel, specify a duration in simulation time for which you would like your simulation to run.
By default, results are stored in a folder/directory structure called <a string of integers e.g. 12345678>/ in the same directory where you select files/folders for simulation.
Upon simulation completion, you will also see a summary page with links to all logfiles and waveforms.
For text output, every simulation generates a text file containing all output that you send to stdout, for example, via print statements.
For waveform dumps, view the waveform on your browser via our custom viewer.
Certainly--simply specify one in the "Results Folder" field when you begin a simulation and instead of a directory named <a string of integers e.g. 12345678>/, the results will be output to <your folder>/
